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mtd: fsl_ifc_nand: use more portable i/o accessors

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in/out_be32 accessors are Power arch centric whereas
ioread/writebe32 are available in other arches.

Since the IFC device registers are annotated big endian in
fsl_ifc.h, the accessor annotations now match, resulting in the
pleasant side-effect of this patch silencing sparse endian
warnings such as the following:

drivers/mtd/nand/fsl_ifc_nand.c:179:19: warning: incorrect type in argument 1 (different base types)
drivers/mtd/nand/fsl_ifc_nand.c:179:19:    expected unsigned int volatile [noderef] [usertype] <asn:2>*addr
drivers/mtd/nand/fsl_ifc_nand.c:179:19:    got restricted __be32 [noderef] <asn:2>*<noident>

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This commit is contained in:
Kim Phillips 2013-01-11 16:23:59 -06:00 committed by Artem Bityutskiy
parent 44fe63fc0f
commit 0c69fb037a
1 changed files with 118 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

231
drivers/mtd/nand/fsl_ifc_nand.c
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@ -176,8 +176,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
ifc_nand_ctrl->page = page_addr; ifc_nand_ctrl->page = page_addr;
/* Program ROW0/COL0 */ /* Program ROW0/COL0 */
out_be32(&ifc->ifc_nand.row0, page_addr); iowrite32be(page_addr, &ifc->ifc_nand.row0);
out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
buf_num = page_addr & priv->bufnum_mask; buf_num = page_addr & priv->bufnum_mask;
@ -239,18 +239,19 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
int i; int i;
/* set the chip select for NAND Transaction */ /* set the chip select for NAND Transaction */
out_be32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT); iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,
&ifc->ifc_nand.nand_csel);
dev_vdbg(priv->dev, dev_vdbg(priv->dev,
"%s: fir0=%08x fcr0=%08x\n", "%s: fir0=%08x fcr0=%08x\n",
__func__, __func__,
in_be32(&ifc->ifc_nand.nand_fir0), ioread32be(&ifc->ifc_nand.nand_fir0),
in_be32(&ifc->ifc_nand.nand_fcr0)); ioread32be(&ifc->ifc_nand.nand_fcr0));
ctrl->nand_stat = 0; ctrl->nand_stat = 0;
/* start read/write seq */ /* start read/write seq */
out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
/* wait for command complete flag or timeout */ /* wait for command complete flag or timeout */
wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
@ -273,7 +274,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
int sector_end = sector + chip->ecc.steps - 1; int sector_end = sector + chip->ecc.steps - 1;
for (i = sector / 4; i <= sector_end / 4; i++) for (i = sector / 4; i <= sector_end / 4; i++)
eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);
for (i = sector; i <= sector_end; i++) { for (i = sector; i <= sector_end; i++) {
errors = check_read_ecc(mtd, ctrl, eccstat, i); errors = check_read_ecc(mtd, ctrl, eccstat, i);
@ -313,31 +314,33 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
/* Program FIR/IFC_NAND_FCR0 for Small/Large page */ /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
if (mtd->writesize > 512) { if (mtd->writesize > 512) {
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); &ifc->ifc_nand.nand_fir0);
out_be32(&ifc->ifc_nand.nand_fir1, 0x0); iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
out_be32(&ifc->ifc_nand.nand_fcr0, iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); &ifc->ifc_nand.nand_fcr0);
} else { } else {
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); &ifc->ifc_nand.nand_fir0);
out_be32(&ifc->ifc_nand.nand_fir1, 0x0); iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
if (oob) if (oob)
out_be32(&ifc->ifc_nand.nand_fcr0, iowrite32be(NAND_CMD_READOOB <<
NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); IFC_NAND_FCR0_CMD0_SHIFT,
&ifc->ifc_nand.nand_fcr0);
else else
out_be32(&ifc->ifc_nand.nand_fcr0, iowrite32be(NAND_CMD_READ0 <<
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); IFC_NAND_FCR0_CMD0_SHIFT,
&ifc->ifc_nand.nand_fcr0);
} }
} }
@ -357,7 +360,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
switch (command) { switch (command) {
/* READ0 read the entire buffer to use hardware ECC. */ /* READ0 read the entire buffer to use hardware ECC. */
case NAND_CMD_READ0: case NAND_CMD_READ0:
out_be32(&ifc->ifc_nand.nand_fbcr, 0); iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
set_addr(mtd, 0, page_addr, 0); set_addr(mtd, 0, page_addr, 0);
ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@ -372,7 +375,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
/* READOOB reads only the OOB because no ECC is performed. */ /* READOOB reads only the OOB because no ECC is performed. */
case NAND_CMD_READOOB: case NAND_CMD_READOOB:
out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
set_addr(mtd, column, page_addr, 1); set_addr(mtd, column, page_addr, 1);
ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@ -388,19 +391,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
if (command == NAND_CMD_PARAM) if (command == NAND_CMD_PARAM)
timing = IFC_FIR_OP_RBCD; timing = IFC_FIR_OP_RBCD;
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (timing << IFC_NAND_FIR0_OP2_SHIFT),
(timing << IFC_NAND_FIR0_OP2_SHIFT)); &ifc->ifc_nand.nand_fir0);
out_be32(&ifc->ifc_nand.nand_fcr0, iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,
command << IFC_NAND_FCR0_CMD0_SHIFT); &ifc->ifc_nand.nand_fcr0);
out_be32(&ifc->ifc_nand.row3, column); iowrite32be(column, &ifc->ifc_nand.row3);
/* /*
* although currently it's 8 bytes for READID, we always read * although currently it's 8 bytes for READID, we always read
* the maximum 256 bytes(for PARAM) * the maximum 256 bytes(for PARAM)
*/ */
out_be32(&ifc->ifc_nand.nand_fbcr, 256); iowrite32be(256, &ifc->ifc_nand.nand_fbcr);
ifc_nand_ctrl->read_bytes = 256; ifc_nand_ctrl->read_bytes = 256;
set_addr(mtd, 0, 0, 0); set_addr(mtd, 0, 0, 0);
@ -415,16 +418,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
/* ERASE2 uses the block and page address from ERASE1 */ /* ERASE2 uses the block and page address from ERASE1 */
case NAND_CMD_ERASE2: case NAND_CMD_ERASE2:
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); &ifc->ifc_nand.nand_fir0);
out_be32(&ifc->ifc_nand.nand_fcr0, iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
(NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
(NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); &ifc->ifc_nand.nand_fcr0);
out_be32(&ifc->ifc_nand.nand_fbcr, 0); iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
ifc_nand_ctrl->read_bytes = 0; ifc_nand_ctrl->read_bytes = 0;
fsl_ifc_run_command(mtd); fsl_ifc_run_command(mtd);
return; return;
@ -440,26 +443,28 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
(NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT); (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be(
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
(IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT)); (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT),
&ifc->ifc_nand.nand_fir0);
} else { } else {
nand_fcr0 = ((NAND_CMD_PAGEPROG << nand_fcr0 = ((NAND_CMD_PAGEPROG <<
IFC_NAND_FCR0_CMD1_SHIFT) | IFC_NAND_FCR0_CMD1_SHIFT) |
(NAND_CMD_SEQIN << (NAND_CMD_SEQIN <<
IFC_NAND_FCR0_CMD2_SHIFT)); IFC_NAND_FCR0_CMD2_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be(
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
out_be32(&ifc->ifc_nand.nand_fir1, &ifc->ifc_nand.nand_fir0);
(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT)); iowrite32be(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT,
&ifc->ifc_nand.nand_fir1);
if (column >= mtd->writesize) if (column >= mtd->writesize)
nand_fcr0 |= nand_fcr0 |=
@ -474,7 +479,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
column -= mtd->writesize; column -= mtd->writesize;
ifc_nand_ctrl->oob = 1; ifc_nand_ctrl->oob = 1;
} }
out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob); set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
return; return;
} }
@ -482,10 +487,11 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
/* PAGEPROG reuses all of the setup from SEQIN and adds the length */ /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
case NAND_CMD_PAGEPROG: { case NAND_CMD_PAGEPROG: {
if (ifc_nand_ctrl->oob) { if (ifc_nand_ctrl->oob) {
out_be32(&ifc->ifc_nand.nand_fbcr, iowrite32be(ifc_nand_ctrl->index -
ifc_nand_ctrl->index - ifc_nand_ctrl->column); ifc_nand_ctrl->column,
&ifc->ifc_nand.nand_fbcr);
} else { } else {
out_be32(&ifc->ifc_nand.nand_fbcr, 0); iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
} }
fsl_ifc_run_command(mtd); fsl_ifc_run_command(mtd);
@ -493,12 +499,12 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
} }
case NAND_CMD_STATUS: case NAND_CMD_STATUS:
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); &ifc->ifc_nand.nand_fir0);
out_be32(&ifc->ifc_nand.nand_fcr0, iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); &ifc->ifc_nand.nand_fcr0);
out_be32(&ifc->ifc_nand.nand_fbcr, 1); iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
set_addr(mtd, 0, 0, 0); set_addr(mtd, 0, 0, 0);
ifc_nand_ctrl->read_bytes = 1; ifc_nand_ctrl->read_bytes = 1;
@ -512,10 +518,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
return; return;
case NAND_CMD_RESET: case NAND_CMD_RESET:
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); &ifc->ifc_nand.nand_fir0);
out_be32(&ifc->ifc_nand.nand_fcr0, iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); &ifc->ifc_nand.nand_fcr0);
fsl_ifc_run_command(mtd); fsl_ifc_run_command(mtd);
return; return;
@ -639,18 +645,18 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
u32 nand_fsr; u32 nand_fsr;
/* Use READ_STATUS command, but wait for the device to be ready */ /* Use READ_STATUS command, but wait for the device to be ready */
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); &ifc->ifc_nand.nand_fir0);
out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
IFC_NAND_FCR0_CMD0_SHIFT); &ifc->ifc_nand.nand_fcr0);
out_be32(&ifc->ifc_nand.nand_fbcr, 1); iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
set_addr(mtd, 0, 0, 0); set_addr(mtd, 0, 0, 0);
ifc_nand_ctrl->read_bytes = 1; ifc_nand_ctrl->read_bytes = 1;
fsl_ifc_run_command(mtd); fsl_ifc_run_command(mtd);
nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr); nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);
/* /*
* The chip always seems to report that it is * The chip always seems to report that it is
@ -744,34 +750,34 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
uint32_t cs = priv->bank; uint32_t cs = priv->bank;
/* Save CSOR and CSOR_ext */ /* Save CSOR and CSOR_ext */
csor = in_be32(&ifc->csor_cs[cs].csor); csor = ioread32be(&ifc->csor_cs[cs].csor);
csor_ext = in_be32(&ifc->csor_cs[cs].csor_ext); csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);
/* chage PageSize 8K and SpareSize 1K*/ /* chage PageSize 8K and SpareSize 1K*/
csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
out_be32(&ifc->csor_cs[cs].csor, csor_8k); iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);
out_be32(&ifc->csor_cs[cs].csor_ext, 0x0000400); iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);
/* READID */ /* READID */
out_be32(&ifc->ifc_nand.nand_fir0, iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); &ifc->ifc_nand.nand_fir0);
out_be32(&ifc->ifc_nand.nand_fcr0, iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); &ifc->ifc_nand.nand_fcr0);
out_be32(&ifc->ifc_nand.row3, 0x0); iowrite32be(0x0, &ifc->ifc_nand.row3);
out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);
/* Program ROW0/COL0 */ /* Program ROW0/COL0 */
out_be32(&ifc->ifc_nand.row0, 0x0); iowrite32be(0x0, &ifc->ifc_nand.row0);
out_be32(&ifc->ifc_nand.col0, 0x0); iowrite32be(0x0, &ifc->ifc_nand.col0);
/* set the chip select for NAND Transaction */ /* set the chip select for NAND Transaction */
out_be32(&ifc->ifc_nand.nand_csel, cs << IFC_NAND_CSEL_SHIFT); iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
/* start read seq */ /* start read seq */
out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
/* wait for command complete flag or timeout */ /* wait for command complete flag or timeout */
wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
@ -781,8 +787,8 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n"); printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
/* Restore CSOR and CSOR_ext */ /* Restore CSOR and CSOR_ext */
out_be32(&ifc->csor_cs[cs].csor, csor); iowrite32be(csor, &ifc->csor_cs[cs].csor);
out_be32(&ifc->csor_cs[cs].csor_ext, csor_ext); iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);
} }
static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
@ -799,7 +805,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
/* fill in nand_chip structure */ /* fill in nand_chip structure */
/* set up function call table */ /* set up function call table */
if ((in_be32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16) if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
chip->read_byte = fsl_ifc_read_byte16; chip->read_byte = fsl_ifc_read_byte16;
else else
chip->read_byte = fsl_ifc_read_byte; chip->read_byte = fsl_ifc_read_byte;
@ -813,13 +819,13 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
chip->bbt_td = &bbt_main_descr; chip->bbt_td = &bbt_main_descr;
chip->bbt_md = &bbt_mirror_descr; chip->bbt_md = &bbt_mirror_descr;
out_be32(&ifc->ifc_nand.ncfgr, 0x0); iowrite32be(0x0, &ifc->ifc_nand.ncfgr);
/* set up nand options */ /* set up nand options */
chip->bbt_options = NAND_BBT_USE_FLASH; chip->bbt_options = NAND_BBT_USE_FLASH;
if (in_be32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) { if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
chip->read_byte = fsl_ifc_read_byte16; chip->read_byte = fsl_ifc_read_byte16;
chip->options |= NAND_BUSWIDTH_16; chip->options |= NAND_BUSWIDTH_16;
} else { } else {
@ -832,7 +838,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
chip->ecc.read_page = fsl_ifc_read_page; chip->ecc.read_page = fsl_ifc_read_page;
chip->ecc.write_page = fsl_ifc_write_page; chip->ecc.write_page = fsl_ifc_write_page;
csor = in_be32(&ifc->csor_cs[priv->bank].csor); csor = ioread32be(&ifc->csor_cs[priv->bank].csor);
/* Hardware generates ECC per 512 Bytes */ /* Hardware generates ECC per 512 Bytes */
chip->ecc.size = 512; chip->ecc.size = 512;
@ -884,7 +890,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
chip->ecc.mode = NAND_ECC_SOFT; chip->ecc.mode = NAND_ECC_SOFT;
} }
ver = in_be32(&ifc->ifc_rev); ver = ioread32be(&ifc->ifc_rev);
if (ver == FSL_IFC_V1_1_0) if (ver == FSL_IFC_V1_1_0)
fsl_ifc_sram_init(priv); fsl_ifc_sram_init(priv);
@ -910,7 +916,7 @@ static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank, static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
phys_addr_t addr) phys_addr_t addr)
{ {
u32 cspr = in_be32(&ifc->cspr_cs[bank].cspr); u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);
if (!(cspr & CSPR_V)) if (!(cspr & CSPR_V))
return 0; return 0;
@ -997,17 +1003,16 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
dev_set_drvdata(priv->dev, priv); dev_set_drvdata(priv->dev, priv);
out_be32(&ifc->ifc_nand.nand_evter_en, iowrite32be(IFC_NAND_EVTER_EN_OPC_EN |
IFC_NAND_EVTER_EN_OPC_EN | IFC_NAND_EVTER_EN_FTOER_EN |
IFC_NAND_EVTER_EN_FTOER_EN | IFC_NAND_EVTER_EN_WPER_EN,
IFC_NAND_EVTER_EN_WPER_EN); &ifc->ifc_nand.nand_evter_en);
/* enable NAND Machine Interrupts */ /* enable NAND Machine Interrupts */
out_be32(&ifc->ifc_nand.nand_evter_intr_en, iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN |
IFC_NAND_EVTER_INTR_OPCIR_EN | IFC_NAND_EVTER_INTR_FTOERIR_EN |
IFC_NAND_EVTER_INTR_FTOERIR_EN | IFC_NAND_EVTER_INTR_WPERIR_EN,
IFC_NAND_EVTER_INTR_WPERIR_EN); &ifc->ifc_nand.nand_evter_intr_en);
priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start); priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
if (!priv->mtd.name) { if (!priv->mtd.name) {
ret = -ENOMEM; ret = -ENOMEM;