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drm/radeon/kms: r600/r700 disable irq at suspend
To avoid hw doing anythings after we disabled PCIE GART, fully disable IRQ at suspend. Also cleanup a bit the ih structure and process function. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
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@ -1954,6 +1954,7 @@ int r600_suspend(struct radeon_device *rdev)
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/* FIXME: we should wait for ring to be empty */
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r600_cp_stop(rdev);
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rdev->cp.ready = false;
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r600_irq_suspend(rdev);
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r600_wb_disable(rdev);
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r600_pcie_gart_disable(rdev);
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/* unpin shaders bo */
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@ -2200,14 +2201,14 @@ void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
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rb_bufsz = drm_order(ring_size / 4);
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ring_size = (1 << rb_bufsz) * 4;
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rdev->ih.ring_size = ring_size;
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rdev->ih.align_mask = 4 - 1;
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rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
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rdev->ih.rptr = 0;
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}
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static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
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static int r600_ih_ring_alloc(struct radeon_device *rdev)
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{
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int r;
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rdev->ih.ring_size = ring_size;
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/* Allocate ring buffer */
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if (rdev->ih.ring_obj == NULL) {
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r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
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@ -2237,9 +2238,6 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
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return r;
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}
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}
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rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
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rdev->ih.rptr = 0;
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return 0;
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}
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@ -2389,7 +2387,7 @@ int r600_irq_init(struct radeon_device *rdev)
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u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
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/* allocate ring */
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ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size);
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ret = r600_ih_ring_alloc(rdev);
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if (ret)
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return ret;
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@ -2452,10 +2450,15 @@ int r600_irq_init(struct radeon_device *rdev)
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return ret;
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}
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void r600_irq_fini(struct radeon_device *rdev)
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void r600_irq_suspend(struct radeon_device *rdev)
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{
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r600_disable_interrupts(rdev);
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r600_rlc_stop(rdev);
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}
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void r600_irq_fini(struct radeon_device *rdev)
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{
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r600_irq_suspend(rdev);
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r600_ih_ring_fini(rdev);
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}
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@ -2648,9 +2651,7 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
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tmp |= IH_WPTR_OVERFLOW_CLEAR;
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WREG32(IH_RB_CNTL, tmp);
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}
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wptr = wptr & WPTR_OFFSET_MASK;
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return wptr;
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return (wptr & rdev->ih.ptr_mask);
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}
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/* r600 IV Ring
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@ -2686,7 +2687,6 @@ int r600_irq_process(struct radeon_device *rdev)
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u32 wptr = r600_get_ih_wptr(rdev);
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u32 rptr = rdev->ih.rptr;
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u32 src_id, src_data;
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u32 last_entry = rdev->ih.ring_size - 16;
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u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
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unsigned long flags;
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bool queue_hotplug = false;
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@ -2820,10 +2820,8 @@ restart_ih:
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}
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/* wptr/rptr are in bytes! */
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if (rptr == last_entry)
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rptr = 0;
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else
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rptr += 16;
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rptr += 16;
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rptr &= rdev->ih.ptr_mask;
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}
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/* make sure wptr hasn't changed while processing */
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wptr = r600_get_ih_wptr(rdev);
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@ -410,7 +410,6 @@ struct r600_ih {
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unsigned wptr_old;
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unsigned ring_size;
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uint64_t gpu_addr;
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uint32_t align_mask;
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uint32_t ptr_mask;
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spinlock_t lock;
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bool enabled;
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@ -1162,7 +1161,8 @@ extern int r600_irq_init(struct radeon_device *rdev);
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extern void r600_irq_fini(struct radeon_device *rdev);
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extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
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extern int r600_irq_set(struct radeon_device *rdev);
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extern void r600_irq_suspend(struct radeon_device *rdev);
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/* r600 audio */
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extern int r600_audio_init(struct radeon_device *rdev);
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extern int r600_audio_tmds_index(struct drm_encoder *encoder);
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extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
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@ -968,6 +968,7 @@ int rv770_suspend(struct radeon_device *rdev)
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/* FIXME: we should wait for ring to be empty */
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r700_cp_stop(rdev);
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rdev->cp.ready = false;
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r600_irq_suspend(rdev);
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r600_wb_disable(rdev);
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rv770_pcie_gart_disable(rdev);
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/* unpin shaders bo */
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