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gpio/mxs: adopt irq_domain support for mxs gpio driver
Remove irq_domain_add_legacy call from mach-mxs.c and have the gpio driver adopt irqdomain support, so that we can have the mapping between gpio and irq number available without using virtual_irq_start and MXS_GPIO_IRQ_START. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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d9875690d9
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0b76c54121
@ -113,20 +113,8 @@ static int __init mxs_icoll_add_irq_domain(struct device_node *np,
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return 0;
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}
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static int __init mxs_gpio_add_irq_domain(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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static int gpio_irq_base = MXS_GPIO_IRQ_START;
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irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
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gpio_irq_base += 32;
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return 0;
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}
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static const struct of_device_id mxs_irq_match[] __initconst = {
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{ .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
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{ .compatible = "fsl,mxs-gpio", .data = mxs_gpio_add_irq_domain, },
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{ /* sentinel */ }
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};
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@ -24,6 +24,7 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/gpio.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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@ -52,8 +53,6 @@
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#define GPIO_INT_LEV_MASK (1 << 0)
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#define GPIO_INT_POL_MASK (1 << 1)
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#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START)
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enum mxs_gpio_id {
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IMX23_GPIO,
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IMX28_GPIO,
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@ -63,7 +62,7 @@ struct mxs_gpio_port {
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void __iomem *base;
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int id;
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int irq;
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int virtual_irq_start;
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struct irq_domain *domain;
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struct bgpio_chip bgc;
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enum mxs_gpio_id devid;
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};
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@ -82,8 +81,7 @@ static inline int is_imx28_gpio(struct mxs_gpio_port *port)
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static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
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{
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u32 gpio = irq_to_gpio(d->irq);
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u32 pin_mask = 1 << (gpio & 31);
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u32 pin_mask = 1 << d->hwirq;
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxs_gpio_port *port = gc->private;
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void __iomem *pin_addr;
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@ -120,7 +118,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
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else
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writel(pin_mask, pin_addr + MXS_CLR);
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writel(1 << (gpio & 0x1f),
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writel(pin_mask,
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port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
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return 0;
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@ -131,7 +129,6 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 irq_stat;
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struct mxs_gpio_port *port = irq_get_handler_data(irq);
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u32 gpio_irq_no_base = port->virtual_irq_start;
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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@ -140,7 +137,7 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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while (irq_stat != 0) {
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int irqoffset = fls(irq_stat) - 1;
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generic_handle_irq(gpio_irq_no_base + irqoffset);
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generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
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irq_stat &= ~(1 << irqoffset);
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}
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}
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@ -167,12 +164,12 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
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return 0;
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}
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static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
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static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
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gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
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port->base, handle_level_irq);
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gc->private = port;
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@ -194,7 +191,7 @@ static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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struct mxs_gpio_port *port =
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container_of(bgc, struct mxs_gpio_port, bgc);
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return port->virtual_irq_start + offset;
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return irq_find_mapping(port->domain, offset);
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}
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static struct platform_device_id mxs_gpio_ids[] = {
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@ -226,6 +223,7 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
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static void __iomem *base;
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struct mxs_gpio_port *port;
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struct resource *iores = NULL;
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int irq_base;
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int err;
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port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
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@ -241,7 +239,6 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
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port->id = pdev->id;
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port->devid = pdev->id_entry->driver_data;
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}
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port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
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port->irq = platform_get_irq(pdev, 0);
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if (port->irq < 0)
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@ -275,8 +272,19 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
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/* clear address has to be used to clear IRQSTAT bits */
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writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
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irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
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if (irq_base < 0)
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return irq_base;
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port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (!port->domain) {
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err = -ENODEV;
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goto out_irqdesc_free;
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}
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/* gpio-mxs can be a generic irq chip */
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mxs_gpio_init_gc(port);
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mxs_gpio_init_gc(port, irq_base);
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/* setup one handler for each entry */
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irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
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@ -287,18 +295,22 @@ static int __devinit mxs_gpio_probe(struct platform_device *pdev)
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port->base + PINCTRL_DOUT(port), NULL,
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port->base + PINCTRL_DOE(port), NULL, 0);
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if (err)
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return err;
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goto out_irqdesc_free;
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port->bgc.gc.to_irq = mxs_gpio_to_irq;
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port->bgc.gc.base = port->id * 32;
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err = gpiochip_add(&port->bgc.gc);
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if (err) {
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bgpio_remove(&port->bgc);
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return err;
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}
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if (err)
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goto out_bgpio_remove;
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return 0;
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out_bgpio_remove:
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bgpio_remove(&port->bgc);
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out_irqdesc_free:
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irq_free_descs(irq_base, 32);
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return err;
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}
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static struct platform_driver mxs_gpio_driver = {
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