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x86: move 32bit related functions together
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu
Ingo Molnar
parent
01b2e16a7a
commit
0a488a53d7
@ -22,6 +22,8 @@
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#include "cpu.h"
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static struct cpu_dev *this_cpu __cpuinitdata;
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DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
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[GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
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[GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
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@ -58,6 +60,109 @@ DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
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} };
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EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
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static int cachesize_override __cpuinitdata = -1;
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static int disable_x86_serial_nr __cpuinitdata = 1;
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static int __init cachesize_setup(char *str)
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{
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get_option(&str, &cachesize_override);
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return 1;
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}
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__setup("cachesize=", cachesize_setup);
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/*
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* Naming convention should be: <Name> [(<Codename>)]
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* This table only is used unless init_<vendor>() below doesn't set it;
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* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
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*
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*/
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/* Look up CPU names by table lookup. */
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static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
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{
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struct cpu_model_info *info;
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if (c->x86_model >= 16)
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return NULL; /* Range check */
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if (!this_cpu)
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return NULL;
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info = this_cpu->c_models;
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while (info && info->family) {
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if (info->family == c->x86)
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return info->model_names[c->x86_model];
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info++;
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}
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return NULL; /* Not found */
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}
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static int __init x86_fxsr_setup(char *s)
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{
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setup_clear_cpu_cap(X86_FEATURE_FXSR);
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setup_clear_cpu_cap(X86_FEATURE_XMM);
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return 1;
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}
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__setup("nofxsr", x86_fxsr_setup);
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static int __init x86_sep_setup(char *s)
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{
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setup_clear_cpu_cap(X86_FEATURE_SEP);
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return 1;
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}
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__setup("nosep", x86_sep_setup);
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(u32 flag)
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{
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u32 f1, f2;
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asm("pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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return ((f1^f2) & flag) != 0;
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}
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/* Probe for the CPUID instruction */
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static int __cpuinit have_cpuid_p(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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{
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if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
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/* Disable processor serial number */
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unsigned long lo, hi;
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rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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lo |= 0x200000;
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wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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printk(KERN_NOTICE "CPU serial number disabled.\n");
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clear_cpu_cap(c, X86_FEATURE_PN);
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/* Disabling the serial number may affect the cpuid level */
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c->cpuid_level = cpuid_eax(0);
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}
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}
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static int __init x86_serial_nr_setup(char *s)
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{
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disable_x86_serial_nr = 0;
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return 1;
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}
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__setup("serialnumber", x86_serial_nr_setup);
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__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
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/* Current gdt points %fs at the "master" per-cpu area: after this,
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@ -72,9 +177,6 @@ void switch_to_new_gdt(void)
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asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
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}
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static int cachesize_override __cpuinitdata = -1;
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static int disable_x86_serial_nr __cpuinitdata = 1;
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static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
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static void __cpuinit default_init(struct cpuinfo_x86 *c)
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@ -95,14 +197,6 @@ static struct cpu_dev __cpuinitdata default_cpu = {
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.c_vendor = "Unknown",
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.c_x86_vendor = X86_VENDOR_UNKNOWN,
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};
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static struct cpu_dev *this_cpu __cpuinitdata;
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static int __init cachesize_setup(char *str)
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{
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get_option(&str, &cachesize_override);
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return 1;
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}
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__setup("cachesize=", cachesize_setup);
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int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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{
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@ -133,7 +227,6 @@ int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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return 1;
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}
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void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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{
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unsigned int n, dummy, ebx, ecx, edx, l2size;
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@ -150,7 +243,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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if (n < 0x80000006) /* Some chips just has a large L1. */
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return;
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ecx = cpuid_ecx(0x80000006);
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cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
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l2size = ecx >> 16;
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/* do processor-specific cache resizing */
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@ -167,48 +260,23 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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c->x86_cache_size = l2size;
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printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
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l2size, ecx & 0xFF);
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}
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/*
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* Naming convention should be: <Name> [(<Codename>)]
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* This table only is used unless init_<vendor>() below doesn't set it;
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* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
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*
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*/
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/* Look up CPU names by table lookup. */
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static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
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{
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struct cpu_model_info *info;
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if (c->x86_model >= 16)
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return NULL; /* Range check */
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if (!this_cpu)
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return NULL;
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info = this_cpu->c_models;
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while (info && info->family) {
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if (info->family == c->x86)
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return info->model_names[c->x86_model];
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info++;
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}
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return NULL; /* Not found */
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l2size, ecx & 0xFF);
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}
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#ifdef CONFIG_X86_HT
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void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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{
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u32 eax, ebx, ecx, edx;
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int index_msb, core_bits;
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u32 eax, ebx, ecx, edx;
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int index_msb, core_bits;
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if (!cpu_has(c, X86_FEATURE_HT))
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return;
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if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
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goto out;
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cpuid(1, &eax, &ebx, &ecx, &edx);
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if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
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return;
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smp_num_siblings = (ebx & 0xff0000) >> 16;
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if (smp_num_siblings == 1) {
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@ -225,8 +293,6 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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index_msb = get_count_order(smp_num_siblings);
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c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
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printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
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c->phys_proc_id);
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smp_num_siblings = smp_num_siblings / c->x86_max_cores;
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@ -236,10 +302,14 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
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((1 << core_bits) - 1);
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}
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if (c->x86_max_cores > 1)
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printk(KERN_INFO "CPU: Processor Core ID: %d\n",
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c->cpu_core_id);
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out:
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if ((c->x86_max_cores * smp_num_siblings) > 1) {
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printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
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c->phys_proc_id);
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printk(KERN_INFO "CPU: Processor Core ID: %d\n",
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c->cpu_core_id);
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}
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}
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#endif
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@ -273,52 +343,6 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
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this_cpu = &default_cpu;
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}
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static int __init x86_fxsr_setup(char *s)
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{
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setup_clear_cpu_cap(X86_FEATURE_FXSR);
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setup_clear_cpu_cap(X86_FEATURE_XMM);
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return 1;
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}
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__setup("nofxsr", x86_fxsr_setup);
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static int __init x86_sep_setup(char *s)
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{
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setup_clear_cpu_cap(X86_FEATURE_SEP);
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return 1;
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}
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__setup("nosep", x86_sep_setup);
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(u32 flag)
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{
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u32 f1, f2;
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asm("pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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return ((f1^f2) & flag) != 0;
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}
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/* Probe for the CPUID instruction */
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static int __cpuinit have_cpuid_p(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
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{
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/* Get vendor name */
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@ -380,16 +404,16 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
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*/
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static void __init early_identify_cpu(struct cpuinfo_x86 *c)
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{
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c->x86_cache_alignment = 32;
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c->x86_clflush_size = 32;
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c->x86_cache_alignment = c->x86_clflush_size;
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if (!have_cpuid_p())
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return;
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c->extended_cpuid_level = 0;
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memset(&c->x86_capability, 0, sizeof c->x86_capability);
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c->extended_cpuid_level = 0;
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cpu_detect(c);
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get_cpu_vendor(c);
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@ -487,31 +511,6 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
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detect_nopl(c);
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}
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static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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{
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if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
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/* Disable processor serial number */
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unsigned long lo, hi;
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rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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lo |= 0x200000;
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wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
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printk(KERN_NOTICE "CPU serial number disabled.\n");
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clear_cpu_cap(c, X86_FEATURE_PN);
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/* Disabling the serial number may affect the cpuid level */
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c->cpuid_level = cpuid_eax(0);
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}
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}
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static int __init x86_serial_nr_setup(char *s)
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{
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disable_x86_serial_nr = 0;
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return 1;
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}
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__setup("serialnumber", x86_serial_nr_setup);
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/*
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* This does the hard work of actually picking apart the CPU stuff...
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*/
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@ -37,6 +37,8 @@
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#include "cpu.h"
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static struct cpu_dev *this_cpu __cpuinitdata;
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/* We need valid kernel segments for data and code in long mode too
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* IRET will check the segment types kkeil 2000/10/28
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* Also sysret mandates a special GDT layout
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@ -78,7 +80,6 @@ static struct cpu_dev __cpuinitdata default_cpu = {
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.c_vendor = "Unknown",
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.c_x86_vendor = X86_VENDOR_UNKNOWN,
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};
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static struct cpu_dev *this_cpu __cpuinitdata;
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int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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{
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@ -112,7 +113,7 @@ int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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{
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unsigned int n, dummy, ebx, ecx, edx;
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unsigned int n, dummy, ebx, ecx, edx, l2size;
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n = c->extended_cpuid_level;
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@ -125,15 +126,17 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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c->x86_tlbsize = 0;
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}
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if (n >= 0x80000006) {
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cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
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ecx = cpuid_ecx(0x80000006);
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c->x86_cache_size = ecx >> 16;
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c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
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if (n < 0x80000006) /* Some chips just has a large L1. */
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return;
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printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
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c->x86_cache_size, ecx & 0xFF);
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}
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cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
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l2size = ecx >> 16;
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c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
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c->x86_cache_size = l2size;
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printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
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l2size, ecx & 0xFF);
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}
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void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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@ -142,14 +145,13 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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u32 eax, ebx, ecx, edx;
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int index_msb, core_bits;
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cpuid(1, &eax, &ebx, &ecx, &edx);
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if (!cpu_has(c, X86_FEATURE_HT))
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return;
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if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
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goto out;
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cpuid(1, &eax, &ebx, &ecx, &edx);
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smp_num_siblings = (ebx & 0xff0000) >> 16;
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if (smp_num_siblings == 1) {
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@ -175,6 +177,7 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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c->cpu_core_id = phys_pkg_id(index_msb) &
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((1 << core_bits) - 1);
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}
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out:
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if ((c->x86_max_cores * smp_num_siblings) > 1) {
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printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
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@ -182,7 +185,6 @@ out:
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printk(KERN_INFO "CPU: Processor Core ID: %d\n",
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c->cpu_core_id);
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}
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#endif
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}
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@ -405,10 +407,10 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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c->x86_model = c->x86_mask = 0; /* So far unknown... */
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c->x86_vendor_id[0] = '\0'; /* Unset */
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c->x86_model_id[0] = '\0'; /* Unset */
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c->x86_clflush_size = 64;
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c->x86_cache_alignment = c->x86_clflush_size;
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c->x86_max_cores = 1;
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c->x86_coreid_bits = 0;
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c->x86_clflush_size = 64;
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c->x86_cache_alignment = c->x86_clflush_size;
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memset(&c->x86_capability, 0, sizeof c->x86_capability);
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generic_identify(c);
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