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mtd: spi-nor: Move ISSI bits out of core.c
Create a SPI NOR manufacturer driver for ISSI chips, and move the ISSI definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
This commit is contained in:
Boris Brezillon
Tudor Ambarus
parent
aa6351877f
commit
0a37198183
@ -8,4 +8,5 @@ spi-nor-objs += everspin.o
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spi-nor-objs += fujitsu.o
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spi-nor-objs += gigadevice.o
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spi-nor-objs += intel.o
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spi-nor-objs += issi.o
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obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
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@ -2007,28 +2007,6 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
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return 0;
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}
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static int
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is25lp256_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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/*
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* IS25LP256 supports 4B opcodes, but the BFPT advertises a
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* BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.
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* Overwrite the address width advertised by the BFPT.
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*/
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if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
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BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
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nor->addr_width = 4;
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return 0;
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}
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static struct spi_nor_fixups is25lp256_fixups = {
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.post_bfpt = is25lp256_post_bfpt_fixups,
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};
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static int
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mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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@ -2066,35 +2044,6 @@ static struct spi_nor_fixups mx25l25635_fixups = {
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* old entries may be missing 4K flag.
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*/
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static const struct flash_info spi_nor_ids[] = {
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/* ISSI */
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{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
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{ "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES)
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.fixups = &is25lp256_fixups },
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{ "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES)
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.fixups = &is25lp256_fixups },
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/* Macronix */
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{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
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{ "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
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@ -2175,11 +2124,6 @@ static const struct flash_info spi_nor_ids[] = {
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SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
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SPI_NOR_4B_OPCODES) },
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/* PMC */
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{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
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{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
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{ "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
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/* Spansion/Cypress -- single (large) sector size only, at least
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* for the chips listed here (without boot sectors).
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*/
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@ -2368,6 +2312,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
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&spi_nor_fujitsu,
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&spi_nor_gigadevice,
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&spi_nor_intel,
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&spi_nor_issi,
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};
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static const struct flash_info *
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@ -3147,11 +3092,6 @@ static int spi_nor_setup(struct spi_nor *nor,
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return nor->params.setup(nor, hwcaps);
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}
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static void issi_set_default_init(struct spi_nor *nor)
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{
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nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
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}
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static void macronix_set_default_init(struct spi_nor *nor)
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{
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nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
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@ -3185,10 +3125,6 @@ static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
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{
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/* Init flash parameters based on MFR */
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switch (JEDEC_MFR(nor->info)) {
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case SNOR_MFR_ISSI:
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issi_set_default_init(nor);
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break;
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case SNOR_MFR_MACRONIX:
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macronix_set_default_init(nor);
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break;
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@ -174,6 +174,7 @@ extern const struct spi_nor_manufacturer spi_nor_everspin;
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extern const struct spi_nor_manufacturer spi_nor_fujitsu;
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extern const struct spi_nor_manufacturer spi_nor_gigadevice;
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extern const struct spi_nor_manufacturer spi_nor_intel;
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extern const struct spi_nor_manufacturer spi_nor_issi;
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int spi_nor_write_enable(struct spi_nor *nor);
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int spi_nor_write_disable(struct spi_nor *nor);
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83
drivers/mtd/spi-nor/issi.c
Normal file
83
drivers/mtd/spi-nor/issi.c
Normal file
@ -0,0 +1,83 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static int
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is25lp256_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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/*
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* IS25LP256 supports 4B opcodes, but the BFPT advertises a
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* BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.
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* Overwrite the address width advertised by the BFPT.
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*/
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if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
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BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
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nor->addr_width = 4;
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return 0;
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}
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static struct spi_nor_fixups is25lp256_fixups = {
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.post_bfpt = is25lp256_post_bfpt_fixups,
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};
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static const struct flash_info issi_parts[] = {
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/* ISSI */
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{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
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{ "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25lp016d", INFO(0x9d6015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25lp080d", INFO(0x9d6014, 0, 64 * 1024, 16,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES)
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.fixups = &is25lp256_fixups },
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{ "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES)
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.fixups = &is25lp256_fixups },
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/* PMC */
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{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
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{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
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{ "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
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};
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static void issi_default_init(struct spi_nor *nor)
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{
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nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable;
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}
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static const struct spi_nor_fixups issi_fixups = {
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.default_init = issi_default_init,
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};
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const struct spi_nor_manufacturer spi_nor_issi = {
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.name = "issi",
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.parts = issi_parts,
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.nparts = ARRAY_SIZE(issi_parts),
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.fixups = &issi_fixups,
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};
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