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x86: Remove CONFIG_X86_OOSTORE
This was an optimization that made memcpy type benchmarks a little faster on ancient (Circa 1998) IDT Winchip CPUs. In real-life workloads, it wasn't even noticable, and I doubt anyone is running benchmarks on 16 year old silicon any more. Given this code has likely seen very little use over the last decade, let's just remove it. Signed-off-by: Dave Jones <davej@fedoraproject.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Dave Jones
Linus Torvalds
parent
8712a00514
commit
09df7c4c80
@ -341,10 +341,6 @@ config X86_USE_3DNOW
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def_bool y
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depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
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config X86_OOSTORE
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def_bool y
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depends on (MWINCHIP3D || MWINCHIPC6) && MTRR
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#
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# P6_NOPs are a relatively minor optimization that require a family >=
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# 6 processor, except that it is broken on certain VIA chips.
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@ -85,11 +85,7 @@
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#else
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# define smp_rmb() barrier()
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#endif
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#ifdef CONFIG_X86_OOSTORE
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# define smp_wmb() wmb()
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#else
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# define smp_wmb() barrier()
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#endif
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() read_barrier_depends()
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#else /* !SMP */
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@ -100,7 +96,7 @@
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#define set_mb(var, value) do { var = value; barrier(); } while (0)
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#endif /* SMP */
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#if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
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#if defined(CONFIG_X86_PPRO_FENCE)
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/*
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* For either of these options x86 doesn't have a strong TSO memory
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@ -237,7 +237,7 @@ memcpy_toio(volatile void __iomem *dst, const void *src, size_t count)
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static inline void flush_write_buffers(void)
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{
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#if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
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#if defined(CONFIG_X86_PPRO_FENCE)
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asm volatile("lock; addl $0,0(%%esp)": : :"memory");
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#endif
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}
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@ -26,10 +26,9 @@
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# define LOCK_PTR_REG "D"
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#endif
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#if defined(CONFIG_X86_32) && \
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(defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
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#if defined(CONFIG_X86_32) && (defined(CONFIG_X86_PPRO_FENCE))
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/*
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* On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
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* On PPro SMP, we use a locked operation to unlock
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* (PPro errata 66, 92)
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*/
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# define UNLOCK_LOCK_PREFIX LOCK_PREFIX
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@ -8,236 +8,6 @@
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#include "cpu.h"
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#ifdef CONFIG_X86_OOSTORE
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static u32 power2(u32 x)
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{
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u32 s = 1;
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while (s <= x)
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s <<= 1;
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return s >>= 1;
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}
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/*
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* Set up an actual MCR
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*/
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static void centaur_mcr_insert(int reg, u32 base, u32 size, int key)
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{
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u32 lo, hi;
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hi = base & ~0xFFF;
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lo = ~(size-1); /* Size is a power of 2 so this makes a mask */
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lo &= ~0xFFF; /* Remove the ctrl value bits */
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lo |= key; /* Attribute we wish to set */
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wrmsr(reg+MSR_IDT_MCR0, lo, hi);
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mtrr_centaur_report_mcr(reg, lo, hi); /* Tell the mtrr driver */
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}
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/*
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* Figure what we can cover with MCR's
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*
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* Shortcut: We know you can't put 4Gig of RAM on a winchip
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*/
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static u32 ramtop(void)
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{
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u32 clip = 0xFFFFFFFFUL;
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u32 top = 0;
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int i;
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for (i = 0; i < e820.nr_map; i++) {
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unsigned long start, end;
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if (e820.map[i].addr > 0xFFFFFFFFUL)
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continue;
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/*
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* Don't MCR over reserved space. Ignore the ISA hole
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* we frob around that catastrophe already
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*/
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if (e820.map[i].type == E820_RESERVED) {
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if (e820.map[i].addr >= 0x100000UL &&
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e820.map[i].addr < clip)
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clip = e820.map[i].addr;
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continue;
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}
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start = e820.map[i].addr;
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end = e820.map[i].addr + e820.map[i].size;
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if (start >= end)
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continue;
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if (end > top)
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top = end;
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}
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/*
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* Everything below 'top' should be RAM except for the ISA hole.
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* Because of the limited MCR's we want to map NV/ACPI into our
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* MCR range for gunk in RAM
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*
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* Clip might cause us to MCR insufficient RAM but that is an
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* acceptable failure mode and should only bite obscure boxes with
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* a VESA hole at 15Mb
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*
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* The second case Clip sometimes kicks in is when the EBDA is marked
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* as reserved. Again we fail safe with reasonable results
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*/
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if (top > clip)
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top = clip;
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return top;
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}
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/*
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* Compute a set of MCR's to give maximum coverage
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*/
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static int centaur_mcr_compute(int nr, int key)
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{
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u32 mem = ramtop();
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u32 root = power2(mem);
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u32 base = root;
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u32 top = root;
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u32 floor = 0;
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int ct = 0;
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while (ct < nr) {
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u32 fspace = 0;
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u32 high;
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u32 low;
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/*
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* Find the largest block we will fill going upwards
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*/
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high = power2(mem-top);
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/*
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* Find the largest block we will fill going downwards
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*/
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low = base/2;
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/*
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* Don't fill below 1Mb going downwards as there
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* is an ISA hole in the way.
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*/
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if (base <= 1024*1024)
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low = 0;
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/*
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* See how much space we could cover by filling below
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* the ISA hole
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*/
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if (floor == 0)
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fspace = 512*1024;
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else if (floor == 512*1024)
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fspace = 128*1024;
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/* And forget ROM space */
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/*
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* Now install the largest coverage we get
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*/
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if (fspace > high && fspace > low) {
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centaur_mcr_insert(ct, floor, fspace, key);
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floor += fspace;
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} else if (high > low) {
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centaur_mcr_insert(ct, top, high, key);
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top += high;
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} else if (low > 0) {
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base -= low;
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centaur_mcr_insert(ct, base, low, key);
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} else
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break;
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ct++;
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}
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/*
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* We loaded ct values. We now need to set the mask. The caller
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* must do this bit.
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*/
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return ct;
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}
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static void centaur_create_optimal_mcr(void)
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{
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int used;
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int i;
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/*
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* Allocate up to 6 mcrs to mark as much of ram as possible
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* as write combining and weak write ordered.
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*
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* To experiment with: Linux never uses stack operations for
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* mmio spaces so we could globally enable stack operation wc
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*
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* Load the registers with type 31 - full write combining, all
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* writes weakly ordered.
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*/
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used = centaur_mcr_compute(6, 31);
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/*
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* Wipe unused MCRs
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*/
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for (i = used; i < 8; i++)
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wrmsr(MSR_IDT_MCR0+i, 0, 0);
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}
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static void winchip2_create_optimal_mcr(void)
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{
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u32 lo, hi;
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int used;
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int i;
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/*
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* Allocate up to 6 mcrs to mark as much of ram as possible
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* as write combining, weak store ordered.
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*
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* Load the registers with type 25
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* 8 - weak write ordering
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* 16 - weak read ordering
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* 1 - write combining
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*/
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used = centaur_mcr_compute(6, 25);
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/*
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* Mark the registers we are using.
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*/
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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for (i = 0; i < used; i++)
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lo |= 1<<(9+i);
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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/*
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* Wipe unused MCRs
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*/
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for (i = used; i < 8; i++)
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wrmsr(MSR_IDT_MCR0+i, 0, 0);
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}
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/*
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* Handle the MCR key on the Winchip 2.
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*/
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static void winchip2_unprotect_mcr(void)
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{
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u32 lo, hi;
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u32 key;
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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lo &= ~0x1C0; /* blank bits 8-6 */
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key = (lo>>17) & 7;
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lo |= key<<6; /* replace with unlock key */
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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}
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static void winchip2_protect_mcr(void)
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{
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u32 lo, hi;
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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lo &= ~0x1C0; /* blank bits 8-6 */
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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}
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#endif /* CONFIG_X86_OOSTORE */
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#define ACE_PRESENT (1 << 6)
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#define ACE_ENABLED (1 << 7)
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#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
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@ -362,20 +132,6 @@ static void init_centaur(struct cpuinfo_x86 *c)
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fcr_clr = DPDC;
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printk(KERN_NOTICE "Disabling bugged TSC.\n");
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clear_cpu_cap(c, X86_FEATURE_TSC);
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#ifdef CONFIG_X86_OOSTORE
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centaur_create_optimal_mcr();
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/*
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* Enable:
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* write combining on non-stack, non-string
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* write combining on string, all types
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* weak write ordering
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*
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* The C6 original lacks weak read order
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*
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* Note 0x120 is write only on Winchip 1
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*/
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wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
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#endif
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break;
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case 8:
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switch (c->x86_mask) {
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@ -392,40 +148,12 @@ static void init_centaur(struct cpuinfo_x86 *c)
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
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E2MMX|EAMD3D;
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fcr_clr = DPDC;
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#ifdef CONFIG_X86_OOSTORE
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winchip2_unprotect_mcr();
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winchip2_create_optimal_mcr();
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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/*
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* Enable:
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* write combining on non-stack, non-string
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* write combining on string, all types
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* weak write ordering
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*/
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lo |= 31;
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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winchip2_protect_mcr();
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#endif
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break;
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case 9:
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name = "3";
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
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E2MMX|EAMD3D;
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fcr_clr = DPDC;
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#ifdef CONFIG_X86_OOSTORE
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winchip2_unprotect_mcr();
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winchip2_create_optimal_mcr();
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rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
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/*
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* Enable:
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* write combining on non-stack, non-string
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* write combining on string, all types
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* weak write ordering
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*/
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lo |= 31;
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wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
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winchip2_protect_mcr();
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#endif
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break;
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default:
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name = "??";
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@ -40,11 +40,7 @@
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#define smp_rmb() barrier()
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#endif /* CONFIG_X86_PPRO_FENCE */
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#ifdef CONFIG_X86_OOSTORE
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#define smp_wmb() wmb()
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#else /* CONFIG_X86_OOSTORE */
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#define smp_wmb() barrier()
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#endif /* CONFIG_X86_OOSTORE */
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#define smp_read_barrier_depends() read_barrier_depends()
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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