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clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3

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On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one.  Extend struct rcar_gen3_cpg_pll_config to handle
this.  As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca. 0.5 KiB for a generic kernel.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Geert Uytterhoeven 2017-07-19 16:30:45 +02:00
parent 714c53aa2e
commit 09a7dea9d5
4 changed files with 41 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
drivers/clk/renesas/r8a7795-cpg-mssr.c
View File

@ -305,23 +305,23 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult PLL3 mult */
{ 1, 192, 192, },
{ 1, 192, 128, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 192, },
{ 1, 160, 160, },
{ 1, 160, 106, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 160, },
{ 1, 128, 128, },
{ 1, 128, 84, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 128, },
{ 2, 192, 192, },
{ 2, 192, 128, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 192, },
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 192, 1, 192, 1, },
{ 1, 192, 1, 128, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, },
{ 1, 160, 1, 160, 1, },
{ 1, 160, 1, 106, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, },
{ 1, 128, 1, 128, 1, },
{ 1, 128, 1, 84, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, },
{ 2, 192, 1, 192, 1, },
{ 2, 192, 1, 128, 1, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, },
};
static const struct soc_device_attribute r8a7795es1[] __initconst = {

34
drivers/clk/renesas/r8a7796-cpg-mssr.c
View File

@ -277,23 +277,23 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult PLL3 mult */
{ 1, 192, 192, },
{ 1, 192, 128, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 192, },
{ 1, 160, 160, },
{ 1, 160, 106, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 160, },
{ 1, 128, 128, },
{ 1, 128, 84, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 128, },
{ 2, 192, 192, },
{ 2, 192, 128, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 192, },
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 192, 1, 192, 1, },
{ 1, 192, 1, 128, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, },
{ 1, 160, 1, 160, 1, },
{ 1, 160, 1, 106, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, },
{ 1, 128, 1, 128, 1, },
{ 1, 128, 1, 84, 1, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, },
{ 2, 192, 1, 192, 1, },
{ 2, 192, 1, 128, 1, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, },
};
static int __init r8a7796_cpg_mssr_init(struct device *dev)

2
drivers/clk/renesas/rcar-gen3-cpg.c
View File

@ -296,6 +296,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
case CLK_TYPE_GEN3_PLL1:
mult = cpg_pll_config->pll1_mult;
div = cpg_pll_config->pll1_div;
break;
case CLK_TYPE_GEN3_PLL2:
@ -313,6 +314,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
case CLK_TYPE_GEN3_PLL3:
mult = cpg_pll_config->pll3_mult;
div = cpg_pll_config->pll3_div;
break;
case CLK_TYPE_GEN3_PLL4:

8
drivers/clk/renesas/rcar-gen3-cpg.h
View File

@ -26,9 +26,11 @@ enum rcar_gen3_clk_types {
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
struct rcar_gen3_cpg_pll_config {
unsigned int extal_div;
unsigned int pll1_mult;
unsigned int pll3_mult;
u8 extal_div;
u8 pll1_mult;
u8 pll1_div;
u8 pll3_mult;
u8 pll3_div;
};
#define CPG_RCKCR 0x240