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ARM: dts: r8a7740: Rename the serial port clock to fck

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The clock is really the device functional clock, not the interface
clock. Rename it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Laurent Pinchart 2016-01-29 10:47:34 +01:00 committed by Simon Horman
parent d4be2f1bfd
commit 0995b9a8d6
1 changed files with 9 additions and 9 deletions
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18
arch/arm/boot/dts/r8a7740.dtsi
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@ -214,7 +214,7 @@
reg = <0xe6c40000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
clock-names = "sci_ick";
clock-names = "fck";
power-domains = <&pd_a3sp>;
status = "disabled";
};
@ -224,7 +224,7 @@
reg = <0xe6c50000 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
clock-names = "sci_ick";
clock-names = "fck";
power-domains = <&pd_a3sp>;
status = "disabled";
};
@ -234,7 +234,7 @@
reg = <0xe6c60000 0x100>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
clock-names = "sci_ick";
clock-names = "fck";
power-domains = <&pd_a3sp>;
status = "disabled";
};
@ -244,7 +244,7 @@
reg = <0xe6c70000 0x100>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
clock-names = "sci_ick";
clock-names = "fck";
power-domains = <&pd_a3sp>;
status = "disabled";
};
@ -254,7 +254,7 @@
reg = <0xe6c80000 0x100>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
clock-names = "sci_ick";
clock-names = "fck";
power-domains = <&pd_a3sp>;
status = "disabled";
};
@ -264,7 +264,7 @@
reg = <0xe6cb0000 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
clock-names = "sci_ick";
clock-names = "fck";
power-domains = <&pd_a3sp>;
status = "disabled";
};
@ -274,7 +274,7 @@
reg = <0xe6cc0000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
clock-names = "sci_ick";
clock-names = "fck";
power-domains = <&pd_a3sp>;
status = "disabled";
};
@ -284,7 +284,7 @@
reg = <0xe6cd0000 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
clock-names = "sci_ick";
clock-names = "fck";
power-domains = <&pd_a3sp>;
status = "disabled";
};
@ -294,7 +294,7 @@
reg = <0xe6c30000 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
clock-names = "sci_ick";
clock-names = "fck";
power-domains = <&pd_a3sp>;
status = "disabled";
};