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b43: N-PHY: update init code to match current specs
Previous init path was based on old specs from old driver. Update it as much as possible leaving some TODOs for not implemented functions. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -419,75 +419,196 @@ static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
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//TODO
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}
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/*
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* Init N-PHY
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* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
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*/
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int b43_phy_initn(struct b43_wldev *dev)
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{
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struct ssb_bus *bus = dev->dev->bus;
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struct b43_phy *phy = &dev->phy;
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struct b43_phy_n *nphy = phy->n;
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u8 tx_pwr_state;
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struct nphy_txgains target;
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u16 tmp;
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enum ieee80211_band tmp2;
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bool do_rssi_cal;
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//TODO: Spectral management
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u16 clip[2];
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bool do_cal = false;
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if ((dev->phy.rev >= 3) &&
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(bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
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(b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
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chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
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}
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nphy->deaf_count = 0;
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b43_nphy_tables_init(dev);
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nphy->crsminpwr_adjusted = false;
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nphy->noisevars_adjusted = false;
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/* Clear all overrides */
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if (dev->phy.rev >= 3) {
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b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
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b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
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b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
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b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
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} else {
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b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
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}
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b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
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b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
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if (dev->phy.rev < 6) {
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b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
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b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
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}
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b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
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~(B43_NPHY_RFSEQMODE_CAOVER |
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B43_NPHY_RFSEQMODE_TROVER));
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if (dev->phy.rev >= 3)
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b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
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b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
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tmp = (phy->rev < 2) ? 64 : 59;
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if (dev->phy.rev <= 2) {
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tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
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b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
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~B43_NPHY_BPHY_CTL3_SCALE,
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tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
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}
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b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
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b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
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b43_phy_write(dev, B43_NPHY_TXREALFD, 184);
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b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 200);
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b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 80);
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b43_phy_write(dev, B43_NPHY_C2_BCLIPBKOFF, 511);
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if (bus->sprom.boardflags2_lo & 0x100 ||
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(bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
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bus->boardinfo.type == 0x8B))
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b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
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else
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b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
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b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
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b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
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b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
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//TODO MIMO-Config
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//TODO Update TX/RX chain
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/* TODO MIMO-Config */
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/* TODO Update TX/RX chain */
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if (phy->rev < 2) {
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b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
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b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
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}
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b43_nphy_workarounds(dev);
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b43_nphy_reset_cca(dev);
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ssb_write32(dev->dev, SSB_TMSLOW,
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ssb_read32(dev->dev, SSB_TMSLOW) | B43_TMSLOW_MACPHYCLKEN);
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tmp2 = b43_current_band(dev->wl);
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if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
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(nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
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b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
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b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
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nphy->papd_epsilon_offset[0] << 7);
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b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
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b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
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nphy->papd_epsilon_offset[1] << 7);
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/* TODO N PHY IPA Set TX Dig Filters */
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} else if (phy->rev >= 5) {
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/* TODO N PHY Ext PA Set TX Dig Filters */
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}
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b43_nphy_workarounds(dev);
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/* Reset CCA, in init code it differs a little from standard way */
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/* b43_nphy_bmac_clock_fgc(dev, 1); */
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tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
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b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
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b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
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/* b43_nphy_bmac_clock_fgc(dev, 0); */
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/* TODO N PHY MAC PHY Clock Set with argument 1 */
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/* b43_nphy_pa_override(dev, false); */
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b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
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b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
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/* b43_nphy_pa_override(dev, true); */
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b43_phy_read(dev, B43_NPHY_CLASSCTL); /* dummy read */
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//TODO read core1/2 clip1 thres regs
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/* b43_nphy_classifier(dev, 0, 0); */
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/* b43_nphy_read_clip_detection(dev, clip); */
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tx_pwr_state = nphy->txpwrctrl;
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/* TODO N PHY TX power control with argument 0
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(turning off power control) */
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/* TODO Fix the TX Power Settings */
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/* TODO N PHY TX Power Control Idle TSSI */
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/* TODO N PHY TX Power Control Setup */
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if (1 /* FIXME Band is 2.4GHz */)
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b43_nphy_bphy_init(dev);
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//TODO disable TX power control
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//TODO Fix the TX power settings
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//TODO Init periodic calibration with reason 3
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b43_nphy_rssi_cal(dev, 2);
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b43_nphy_rssi_cal(dev, 0);
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b43_nphy_rssi_cal(dev, 1);
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//TODO get TX gain
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//TODO init superswitch
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//TODO calibrate LO
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//TODO idle TSSI TX pctl
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//TODO TX power control power setup
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//TODO table writes
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//TODO TX power control coefficients
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//TODO enable TX power control
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//TODO control antenna selection
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//TODO init radar detection
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//TODO reset channel if changed
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if (phy->rev >= 3) {
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/* TODO */
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} else {
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/* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
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/* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
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}
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if (nphy->phyrxchain != 3)
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;/* TODO N PHY RX Core Set State with phyrxchain as argument */
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if (nphy->mphase_cal_phase_id > 0)
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;/* TODO PHY Periodic Calibration Multi-Phase Restart */
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do_rssi_cal = false;
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if (phy->rev >= 3) {
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
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do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
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else
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do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
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if (do_rssi_cal)
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;/* b43_nphy_rssi_cal(dev); */
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else
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;/* b43_nphy_restore_rssi_cal(dev); */
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} else {
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/* b43_nphy_rssi_cal(dev); */
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}
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if (!((nphy->measure_hold & 0x6) != 0)) {
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
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do_cal = (nphy->iqcal_chanspec_2G == 0);
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else
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do_cal = (nphy->iqcal_chanspec_5G == 0);
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if (nphy->mute)
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do_cal = false;
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if (do_cal) {
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/* target = b43_nphy_get_tx_gains(dev); */
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if (nphy->antsel_type == 2)
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;/*TODO NPHY Superswitch Init with argument 1*/
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if (nphy->perical != 2) {
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/* b43_nphy_rssi_cal(dev); */
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if (phy->rev >= 3) {
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nphy->cal_orig_pwr_idx[0] =
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nphy->txpwrindex[0].index_internal;
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nphy->cal_orig_pwr_idx[1] =
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nphy->txpwrindex[1].index_internal;
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/* TODO N PHY Pre Calibrate TX Gain */
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/*target = b43_nphy_get_tx_gains(dev)*/
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}
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}
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}
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}
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/*
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if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
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if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
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Call N PHY Save Cal
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else if (nphy->mphase_cal_phase_id == 0)
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N PHY Periodic Calibration with argument 3
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} else {
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b43_nphy_restore_cal(dev);
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}
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*/
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/* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
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/* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
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b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
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b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
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if (phy->rev >= 3 && phy->rev <= 6)
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b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
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/* b43_nphy_tx_lp_fbw(dev); */
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/* TODO N PHY Spur Workaround */
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b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
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return 0;
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