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x86: Remove duplicate TSC DEADLINE MSR definitions
There are two definitions for the TSC deadline MSR in msr-index.h, one with an underscore and one without. Axe one of them and move all the references over to the other one. [ bp: Fixup the MSR define in handle_fastpath_set_msr_irqoff() too. ] Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200305174706.0D6B8EE4@viggo.jf.intel.com
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@ -628,8 +628,6 @@
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_TSCDEADLINE 0x000006e0
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#define MSR_IA32_UCODE_WRITE 0x00000079
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#define MSR_IA32_UCODE_WRITE 0x00000079
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#define MSR_IA32_UCODE_REV 0x0000008b
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#define MSR_IA32_UCODE_REV 0x0000008b
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@ -1288,7 +1288,7 @@ static const u32 emulated_msrs_all[] = {
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MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
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MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
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MSR_IA32_TSC_ADJUST,
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MSR_IA32_TSC_ADJUST,
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MSR_IA32_TSCDEADLINE,
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MSR_IA32_TSC_DEADLINE,
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MSR_IA32_ARCH_CAPABILITIES,
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MSR_IA32_ARCH_CAPABILITIES,
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MSR_IA32_PERF_CAPABILITIES,
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MSR_IA32_PERF_CAPABILITIES,
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MSR_IA32_MISC_ENABLE,
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MSR_IA32_MISC_ENABLE,
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@ -1841,7 +1841,7 @@ fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
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ret = EXIT_FASTPATH_EXIT_HANDLED;
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ret = EXIT_FASTPATH_EXIT_HANDLED;
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}
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}
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break;
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break;
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case MSR_IA32_TSCDEADLINE:
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case MSR_IA32_TSC_DEADLINE:
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data = kvm_read_edx_eax(vcpu);
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data = kvm_read_edx_eax(vcpu);
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if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
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if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
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kvm_skip_emulated_instruction(vcpu);
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kvm_skip_emulated_instruction(vcpu);
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@ -3075,7 +3075,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return kvm_set_apic_base(vcpu, msr_info);
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return kvm_set_apic_base(vcpu, msr_info);
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case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
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case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
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return kvm_x2apic_msr_write(vcpu, msr, data);
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return kvm_x2apic_msr_write(vcpu, msr, data);
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case MSR_IA32_TSCDEADLINE:
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case MSR_IA32_TSC_DEADLINE:
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kvm_set_lapic_tscdeadline_msr(vcpu, data);
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kvm_set_lapic_tscdeadline_msr(vcpu, data);
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break;
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break;
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case MSR_IA32_TSC_ADJUST:
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case MSR_IA32_TSC_ADJUST:
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@ -3437,7 +3437,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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break;
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break;
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case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
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case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
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return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
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return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
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case MSR_IA32_TSCDEADLINE:
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case MSR_IA32_TSC_DEADLINE:
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msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
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msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
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break;
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break;
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case MSR_IA32_TSC_ADJUST:
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case MSR_IA32_TSC_ADJUST:
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@ -628,8 +628,6 @@
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_TSCDEADLINE 0x000006e0
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#define MSR_IA32_UCODE_WRITE 0x00000079
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#define MSR_IA32_UCODE_WRITE 0x00000079
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#define MSR_IA32_UCODE_REV 0x0000008b
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#define MSR_IA32_UCODE_REV 0x0000008b
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@ -15,7 +15,7 @@ x86_msr_index=${arch_x86_header_dir}/msr-index.h
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printf "static const char *x86_MSRs[] = {\n"
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printf "static const char *x86_MSRs[] = {\n"
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regex='^[[:space:]]*#[[:space:]]*define[[:space:]]+MSR_([[:alnum:]][[:alnum:]_]+)[[:space:]]+(0x00000[[:xdigit:]]+)[[:space:]]*.*'
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regex='^[[:space:]]*#[[:space:]]*define[[:space:]]+MSR_([[:alnum:]][[:alnum:]_]+)[[:space:]]+(0x00000[[:xdigit:]]+)[[:space:]]*.*'
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egrep $regex ${x86_msr_index} | egrep -v 'MSR_(ATOM|P[46]|IA32_(TSCDEADLINE|UCODE_REV)|IDT_FCR4)' | \
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egrep $regex ${x86_msr_index} | egrep -v 'MSR_(ATOM|P[46]|IA32_(TSC_DEADLINE|UCODE_REV)|IDT_FCR4)' | \
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sed -r "s/$regex/\2 \1/g" | sort -n | \
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sed -r "s/$regex/\2 \1/g" | sort -n | \
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xargs printf "\t[%s] = \"%s\",\n"
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xargs printf "\t[%s] = \"%s\",\n"
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printf "};\n\n"
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printf "};\n\n"
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