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intel-pinctrl for v5.5-1
* Intel Tigerlake pin controller support has been added. * Miscellaneous fixes to the main and Cherryview drivers. * Refactoring of the context restoring in the main driver. The following is an automated git shortlog grouped by driver: cherryview: - Missed type change to unsigned int - Allocate IRQ chip dynamic - Fix spelling mistake in the comment - Fix irq_valid_mask calculation intel: - Missed type change to unsigned int - Add Intel Tiger Lake pin controller support - Use helper to restore register values on ->resume() - Drop level from warning to debug in intel_restore_hostown() - Introduce intel_restore_intmask() helper - Introduce intel_restore_hostown() helper - Introduce intel_restore_padcfg() helper - Avoid potential glitches if pin is in GPIO mode -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAl3MDXMACgkQb7wzTHR8 rCgcURAAkQ/FizpJUX8z6PNdLopJWnRQ9e2d0KEHsyrXxRm/IbgWhnMx176hhLl1 PN9GXpM8t7KX/m5rf/w9EKHldP0SLeFyWxCyzWJ+NtpjahpNbP/enxMfgWJJjbwA cocmvhXU9oHgiz3VO3DDpUKGkm+yVoYyam1cWlPqLvhDZjHl2okuNfnr6rO59PaB hGnz8fkIk0xUcSE4wJI63I0UaDwm3YVq9oc8Oq1dtWXaoOX7Eqn1ZELGE15oVPDK kAlqzF9A8c9bpxuVkLRGq2i3aB9S5Ci9/UoTykViTZfQJ7qz7FCYtV1M29yAvXvn oOot/5EGw/ZoxVi/ZbjhLA2tcEJM6O3S3iHELPHNaihPOmHycJ0tavgTn89KJBcR lMR8zS1hpqwIx9KRLEVTGViGdGHLbtu6eXJ+j0qNbezrNcXVdJO0yms2HEbCGe+A 6J8Ucpd4HG5GKHKvnLa7bihvjxdizb/WzjRjE0xbFu2h7j1MKS/3LFcStI5fa0a0 G2pcXgFkr4mui/a8nek/EsATu10KkKt6Aam+xg4DPhUeSoxcC3Jo1EzQ/2Tg/TPI 4XRsEmdiTBHFE2re8mZXkp+g4YYA+KpTMyVsKZC389IJ4cuP8YbsqWJKICoObvuM CZ7B9wPHN1qXA04E7YaWz2KgmZQCD8mNbsxHiAyAX99nvtyDxjE= =iLY+ -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.5-1 * Intel Tigerlake pin controller support has been added. * Miscellaneous fixes to the main and Cherryview drivers. * Refactoring of the context restoring in the main driver. The following is an automated git shortlog grouped by driver: cherryview: - Missed type change to unsigned int - Allocate IRQ chip dynamic - Fix spelling mistake in the comment - Fix irq_valid_mask calculation intel: - Missed type change to unsigned int - Add Intel Tiger Lake pin controller support - Use helper to restore register values on ->resume() - Drop level from warning to debug in intel_restore_hostown() - Introduce intel_restore_intmask() helper - Introduce intel_restore_hostown() helper - Introduce intel_restore_padcfg() helper - Avoid potential glitches if pin is in GPIO mode
This commit is contained in:
Linus Walleij
commit
08a96e43e3
@ -115,4 +115,11 @@ config PINCTRL_SUNRISEPOINT
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provides an interface that allows configuring of PCH pins and
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using them as GPIOs.
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config PINCTRL_TIGERLAKE
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tristate "Intel Tiger Lake pinctrl and GPIO driver"
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depends on ACPI
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select PINCTRL_INTEL
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help
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This pinctrl driver provides an interface that allows configuring
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of Intel Tiger Lake PCH pins and using them as GPIOs.
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endif
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@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
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obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
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obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
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obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
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obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o
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@ -147,6 +147,7 @@ struct chv_pin_context {
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* @pctldesc: Pin controller description
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* @pctldev: Pointer to the pin controller device
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* @chip: GPIO chip in this pin controller
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* @irqchip: IRQ chip in this pin controller
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* @regs: MMIO registers
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* @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
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* offset (in GPIO number space)
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@ -162,8 +163,9 @@ struct chv_pinctrl {
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struct pinctrl_desc pctldesc;
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struct pinctrl_dev *pctldev;
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struct gpio_chip chip;
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struct irq_chip irqchip;
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void __iomem *regs;
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unsigned intr_lines[16];
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unsigned int intr_lines[16];
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const struct chv_community *community;
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u32 saved_intmask;
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struct chv_pin_context *saved_pin_context;
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@ -377,7 +379,7 @@ static const struct chv_community southwest_community = {
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.gpio_ranges = southwest_gpio_ranges,
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.ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
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/*
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* Southwest community can benerate GPIO interrupts only for the
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* Southwest community can generate GPIO interrupts only for the
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* first 8 interrupts. The upper half (8-15) can only be used to
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* trigger GPEs.
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*/
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@ -1466,16 +1468,6 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
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return 0;
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}
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static struct irq_chip chv_gpio_irqchip = {
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.name = "chv-gpio",
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.irq_startup = chv_gpio_irq_startup,
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.irq_ack = chv_gpio_irq_ack,
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.irq_mask = chv_gpio_irq_mask,
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.irq_unmask = chv_gpio_irq_unmask,
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.irq_set_type = chv_gpio_irq_type,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static void chv_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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@ -1488,7 +1480,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
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pending = readl(pctrl->regs + CHV_INTSTAT);
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for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
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unsigned irq, offset;
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unsigned int irq, offset;
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offset = pctrl->intr_lines[intr_line];
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irq = irq_find_mapping(gc->irq.domain, offset);
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@ -1559,7 +1551,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
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intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
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if (intsel >= community->nirqs)
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clear_bit(i, valid_mask);
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clear_bit(desc->number, valid_mask);
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}
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}
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@ -1625,7 +1617,15 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
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}
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}
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ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
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pctrl->irqchip.name = "chv-gpio";
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pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
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pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
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pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
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pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
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pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
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pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
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ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,
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handle_bad_irq, IRQ_TYPE_NONE);
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if (ret) {
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dev_err(pctrl->dev, "failed to add IRQ chip\n");
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@ -1642,7 +1642,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
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}
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}
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gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
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gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,
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chv_gpio_irq_handler);
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return 0;
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}
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@ -52,6 +52,7 @@
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#define PADCFG0_GPIROUTNMI BIT(17)
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#define PADCFG0_PMODE_SHIFT 10
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#define PADCFG0_PMODE_MASK GENMASK(13, 10)
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#define PADCFG0_PMODE_GPIO 0
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#define PADCFG0_GPIORXDIS BIT(9)
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#define PADCFG0_GPIOTXDIS BIT(8)
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#define PADCFG0_GPIORXSTATE BIT(1)
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@ -332,7 +333,7 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
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mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
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if (!mode)
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if (mode == PADCFG0_PMODE_GPIO)
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seq_puts(s, "GPIO ");
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else
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seq_printf(s, "mode %d ", mode);
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@ -458,6 +459,11 @@ static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
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writel(value, padcfg0);
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}
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static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
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{
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return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
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}
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static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
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{
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u32 value;
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@ -491,7 +497,20 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
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}
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padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
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/*
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* If pin is already configured in GPIO mode, we assume that
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* firmware provides correct settings. In such case we avoid
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* potential glitches on the pin. Otherwise, for the pin in
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* alternative mode, consumer has to supply respective flags.
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*/
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if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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intel_gpio_set_gpio_mode(padcfg0);
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/* Disable TX buffer and enable RX (this will be input) */
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__intel_gpio_set_direction(padcfg0, true);
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@ -1112,7 +1131,7 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
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pending &= enabled;
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for_each_set_bit(gpp_offset, &pending, padgrp->size) {
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unsigned irq;
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unsigned int irq;
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irq = irq_find_mapping(gc->irq.domain,
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padgrp->gpio_base + gpp_offset);
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@ -1162,7 +1181,7 @@ static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
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return ret;
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}
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static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
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static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
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{
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const struct intel_community *community;
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unsigned int ngpio = 0;
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@ -1576,16 +1595,65 @@ intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
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return requested;
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}
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static u32
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intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value)
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static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
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{
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u32 curr, updated;
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curr = readl(hostown);
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updated = (curr & ~mask) | (value & mask);
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writel(updated, hostown);
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curr = readl(reg);
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return curr;
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updated = (curr & ~mask) | (value & mask);
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if (curr == updated)
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return false;
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writel(updated, reg);
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return true;
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}
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static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
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void __iomem *base, unsigned int gpp, u32 saved)
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{
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const struct intel_community *community = &pctrl->communities[c];
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const struct intel_padgroup *padgrp = &community->gpps[gpp];
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struct device *dev = pctrl->dev;
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u32 requested;
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if (padgrp->gpio_base < 0)
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return;
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requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size);
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if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
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return;
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dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
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}
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static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
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void __iomem *base, unsigned int gpp, u32 saved)
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{
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struct device *dev = pctrl->dev;
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if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
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return;
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dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
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}
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static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
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unsigned int reg, u32 saved)
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{
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u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
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unsigned int n = reg / sizeof(u32);
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struct device *dev = pctrl->dev;
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void __iomem *padcfg;
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padcfg = intel_get_padcfg(pctrl, pin, reg);
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if (!padcfg)
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return;
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if (!intel_gpio_update_reg(padcfg, ~mask, saved))
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return;
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dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
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}
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int intel_pinctrl_resume_noirq(struct device *dev)
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@ -1601,37 +1669,13 @@ int intel_pinctrl_resume_noirq(struct device *dev)
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pads = pctrl->context.pads;
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for (i = 0; i < pctrl->soc->npins; i++) {
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const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
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void __iomem *padcfg;
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u32 val;
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if (!intel_pinctrl_should_save(pctrl, desc->number))
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continue;
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padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
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val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
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if (val != pads[i].padcfg0) {
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writel(pads[i].padcfg0, padcfg);
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dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
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desc->number, readl(padcfg));
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}
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padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
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val = readl(padcfg);
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if (val != pads[i].padcfg1) {
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writel(pads[i].padcfg1, padcfg);
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dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
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desc->number, readl(padcfg));
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}
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padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
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if (padcfg) {
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val = readl(padcfg);
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if (val != pads[i].padcfg2) {
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writel(pads[i].padcfg2, padcfg);
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dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
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desc->number, readl(padcfg));
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}
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}
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intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
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intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
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intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
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}
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communities = pctrl->context.communities;
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@ -1641,30 +1685,12 @@ int intel_pinctrl_resume_noirq(struct device *dev)
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unsigned int gpp;
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base = community->regs + community->ie_offset;
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for (gpp = 0; gpp < community->ngpps; gpp++) {
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writel(communities[i].intmask[gpp], base + gpp * 4);
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dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
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readl(base + gpp * 4));
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}
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for (gpp = 0; gpp < community->ngpps; gpp++)
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intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
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base = community->regs + community->hostown_offset;
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for (gpp = 0; gpp < community->ngpps; gpp++) {
|
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const struct intel_padgroup *padgrp = &community->gpps[gpp];
|
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u32 requested = 0, value = 0;
|
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u32 saved = communities[i].hostown[gpp];
|
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|
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if (padgrp->gpio_base < 0)
|
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continue;
|
||||
|
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requested = intel_gpio_is_requested(&pctrl->chip,
|
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padgrp->gpio_base, padgrp->size);
|
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value = intel_gpio_update_pad_mode(base + gpp * 4,
|
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requested, saved);
|
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if ((value ^ saved) & requested) {
|
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dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n",
|
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i, gpp, value, saved);
|
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}
|
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}
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for (gpp = 0; gpp < community->ngpps; gpp++)
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intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
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}
|
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|
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return 0;
|
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|
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454
drivers/pinctrl/intel/pinctrl-tigerlake.c
Normal file
454
drivers/pinctrl/intel/pinctrl-tigerlake.c
Normal file
@ -0,0 +1,454 @@
|
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// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Intel Tiger Lake PCH pinctrl/GPIO driver
|
||||
*
|
||||
* Copyright (C) 2019, Intel Corporation
|
||||
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
* Mika Westerberg <mika.westerberg@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
|
||||
#include "pinctrl-intel.h"
|
||||
|
||||
#define TGL_PAD_OWN 0x020
|
||||
#define TGL_PADCFGLOCK 0x080
|
||||
#define TGL_HOSTSW_OWN 0x0b0
|
||||
#define TGL_GPI_IS 0x100
|
||||
#define TGL_GPI_IE 0x120
|
||||
|
||||
#define TGL_GPP(r, s, e) \
|
||||
{ \
|
||||
.reg_num = (r), \
|
||||
.base = (s), \
|
||||
.size = ((e) - (s) + 1), \
|
||||
}
|
||||
|
||||
#define TGL_COMMUNITY(s, e, g) \
|
||||
{ \
|
||||
.padown_offset = TGL_PAD_OWN, \
|
||||
.padcfglock_offset = TGL_PADCFGLOCK, \
|
||||
.hostown_offset = TGL_HOSTSW_OWN, \
|
||||
.is_offset = TGL_GPI_IS, \
|
||||
.ie_offset = TGL_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
|
||||
/* Tiger Lake-LP */
|
||||
static const struct pinctrl_pin_desc tgllp_community0_pins[] = {
|
||||
/* GPP_B */
|
||||
PINCTRL_PIN(0, "CORE_VID_0"),
|
||||
PINCTRL_PIN(1, "CORE_VID_1"),
|
||||
PINCTRL_PIN(2, "VRALERTB"),
|
||||
PINCTRL_PIN(3, "CPU_GP_2"),
|
||||
PINCTRL_PIN(4, "CPU_GP_3"),
|
||||
PINCTRL_PIN(5, "ISH_I2C0_SDA"),
|
||||
PINCTRL_PIN(6, "ISH_I2C0_SCL"),
|
||||
PINCTRL_PIN(7, "ISH_I2C1_SDA"),
|
||||
PINCTRL_PIN(8, "ISH_I2C1_SCL"),
|
||||
PINCTRL_PIN(9, "I2C5_SDA"),
|
||||
PINCTRL_PIN(10, "I2C5_SCL"),
|
||||
PINCTRL_PIN(11, "PMCALERTB"),
|
||||
PINCTRL_PIN(12, "SLP_S0B"),
|
||||
PINCTRL_PIN(13, "PLTRSTB"),
|
||||
PINCTRL_PIN(14, "SPKR"),
|
||||
PINCTRL_PIN(15, "GSPI0_CS0B"),
|
||||
PINCTRL_PIN(16, "GSPI0_CLK"),
|
||||
PINCTRL_PIN(17, "GSPI0_MISO"),
|
||||
PINCTRL_PIN(18, "GSPI0_MOSI"),
|
||||
PINCTRL_PIN(19, "GSPI1_CS0B"),
|
||||
PINCTRL_PIN(20, "GSPI1_CLK"),
|
||||
PINCTRL_PIN(21, "GSPI1_MISO"),
|
||||
PINCTRL_PIN(22, "GSPI1_MOSI"),
|
||||
PINCTRL_PIN(23, "SML1ALERTB"),
|
||||
PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
|
||||
/* GPP_T */
|
||||
PINCTRL_PIN(26, "I2C6_SDA"),
|
||||
PINCTRL_PIN(27, "I2C6_SCL"),
|
||||
PINCTRL_PIN(28, "I2C7_SDA"),
|
||||
PINCTRL_PIN(29, "I2C7_SCL"),
|
||||
PINCTRL_PIN(30, "UART4_RXD"),
|
||||
PINCTRL_PIN(31, "UART4_TXD"),
|
||||
PINCTRL_PIN(32, "UART4_RTSB"),
|
||||
PINCTRL_PIN(33, "UART4_CTSB"),
|
||||
PINCTRL_PIN(34, "UART5_RXD"),
|
||||
PINCTRL_PIN(35, "UART5_TXD"),
|
||||
PINCTRL_PIN(36, "UART5_RTSB"),
|
||||
PINCTRL_PIN(37, "UART5_CTSB"),
|
||||
PINCTRL_PIN(38, "UART6_RXD"),
|
||||
PINCTRL_PIN(39, "UART6_TXD"),
|
||||
PINCTRL_PIN(40, "UART6_RTSB"),
|
||||
PINCTRL_PIN(41, "UART6_CTSB"),
|
||||
/* GPP_A */
|
||||
PINCTRL_PIN(42, "ESPI_IO_0"),
|
||||
PINCTRL_PIN(43, "ESPI_IO_1"),
|
||||
PINCTRL_PIN(44, "ESPI_IO_2"),
|
||||
PINCTRL_PIN(45, "ESPI_IO_3"),
|
||||
PINCTRL_PIN(46, "ESPI_CSB"),
|
||||
PINCTRL_PIN(47, "ESPI_CLK"),
|
||||
PINCTRL_PIN(48, "ESPI_RESETB"),
|
||||
PINCTRL_PIN(49, "I2S2_SCLK"),
|
||||
PINCTRL_PIN(50, "I2S2_SFRM"),
|
||||
PINCTRL_PIN(51, "I2S2_TXD"),
|
||||
PINCTRL_PIN(52, "I2S2_RXD"),
|
||||
PINCTRL_PIN(53, "PMC_I2C_SDA"),
|
||||
PINCTRL_PIN(54, "SATAXPCIE_1"),
|
||||
PINCTRL_PIN(55, "PMC_I2C_SCL"),
|
||||
PINCTRL_PIN(56, "USB2_OCB_1"),
|
||||
PINCTRL_PIN(57, "USB2_OCB_2"),
|
||||
PINCTRL_PIN(58, "USB2_OCB_3"),
|
||||
PINCTRL_PIN(59, "DDSP_HPD_C"),
|
||||
PINCTRL_PIN(60, "DDSP_HPD_B"),
|
||||
PINCTRL_PIN(61, "DDSP_HPD_1"),
|
||||
PINCTRL_PIN(62, "DDSP_HPD_2"),
|
||||
PINCTRL_PIN(63, "GPPC_A_21"),
|
||||
PINCTRL_PIN(64, "GPPC_A_22"),
|
||||
PINCTRL_PIN(65, "I2S1_SCLK"),
|
||||
PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup tgllp_community0_gpps[] = {
|
||||
TGL_GPP(0, 0, 25), /* GPP_B */
|
||||
TGL_GPP(1, 26, 41), /* GPP_T */
|
||||
TGL_GPP(2, 42, 66), /* GPP_A */
|
||||
};
|
||||
|
||||
static const struct intel_community tgllp_community0[] = {
|
||||
TGL_COMMUNITY(0, 66, tgllp_community0_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data tgllp_community0_soc_data = {
|
||||
.uid = "0",
|
||||
.pins = tgllp_community0_pins,
|
||||
.npins = ARRAY_SIZE(tgllp_community0_pins),
|
||||
.communities = tgllp_community0,
|
||||
.ncommunities = ARRAY_SIZE(tgllp_community0),
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc tgllp_community1_pins[] = {
|
||||
/* GPP_S */
|
||||
PINCTRL_PIN(0, "SNDW0_CLK"),
|
||||
PINCTRL_PIN(1, "SNDW0_DATA"),
|
||||
PINCTRL_PIN(2, "SNDW1_CLK"),
|
||||
PINCTRL_PIN(3, "SNDW1_DATA"),
|
||||
PINCTRL_PIN(4, "SNDW2_CLK"),
|
||||
PINCTRL_PIN(5, "SNDW2_DATA"),
|
||||
PINCTRL_PIN(6, "SNDW3_CLK"),
|
||||
PINCTRL_PIN(7, "SNDW3_DATA"),
|
||||
/* GPP_H */
|
||||
PINCTRL_PIN(8, "GPPC_H_0"),
|
||||
PINCTRL_PIN(9, "GPPC_H_1"),
|
||||
PINCTRL_PIN(10, "GPPC_H_2"),
|
||||
PINCTRL_PIN(11, "SX_EXIT_HOLDOFFB"),
|
||||
PINCTRL_PIN(12, "I2C2_SDA"),
|
||||
PINCTRL_PIN(13, "I2C2_SCL"),
|
||||
PINCTRL_PIN(14, "I2C3_SDA"),
|
||||
PINCTRL_PIN(15, "I2C3_SCL"),
|
||||
PINCTRL_PIN(16, "I2C4_SDA"),
|
||||
PINCTRL_PIN(17, "I2C4_SCL"),
|
||||
PINCTRL_PIN(18, "SRCCLKREQB_4"),
|
||||
PINCTRL_PIN(19, "SRCCLKREQB_5"),
|
||||
PINCTRL_PIN(20, "M2_SKT2_CFG_0"),
|
||||
PINCTRL_PIN(21, "M2_SKT2_CFG_1"),
|
||||
PINCTRL_PIN(22, "M2_SKT2_CFG_2"),
|
||||
PINCTRL_PIN(23, "M2_SKT2_CFG_3"),
|
||||
PINCTRL_PIN(24, "DDPB_CTRLCLK"),
|
||||
PINCTRL_PIN(25, "DDPB_CTRLDATA"),
|
||||
PINCTRL_PIN(26, "CPU_C10_GATEB"),
|
||||
PINCTRL_PIN(27, "TIME_SYNC_0"),
|
||||
PINCTRL_PIN(28, "IMGCLKOUT_1"),
|
||||
PINCTRL_PIN(29, "IMGCLKOUT_2"),
|
||||
PINCTRL_PIN(30, "IMGCLKOUT_3"),
|
||||
PINCTRL_PIN(31, "IMGCLKOUT_4"),
|
||||
/* GPP_D */
|
||||
PINCTRL_PIN(32, "ISH_GP_0"),
|
||||
PINCTRL_PIN(33, "ISH_GP_1"),
|
||||
PINCTRL_PIN(34, "ISH_GP_2"),
|
||||
PINCTRL_PIN(35, "ISH_GP_3"),
|
||||
PINCTRL_PIN(36, "IMGCLKOUT_0"),
|
||||
PINCTRL_PIN(37, "SRCCLKREQB_0"),
|
||||
PINCTRL_PIN(38, "SRCCLKREQB_1"),
|
||||
PINCTRL_PIN(39, "SRCCLKREQB_2"),
|
||||
PINCTRL_PIN(40, "SRCCLKREQB_3"),
|
||||
PINCTRL_PIN(41, "ISH_SPI_CSB"),
|
||||
PINCTRL_PIN(42, "ISH_SPI_CLK"),
|
||||
PINCTRL_PIN(43, "ISH_SPI_MISO"),
|
||||
PINCTRL_PIN(44, "ISH_SPI_MOSI"),
|
||||
PINCTRL_PIN(45, "ISH_UART0_RXD"),
|
||||
PINCTRL_PIN(46, "ISH_UART0_TXD"),
|
||||
PINCTRL_PIN(47, "ISH_UART0_RTSB"),
|
||||
PINCTRL_PIN(48, "ISH_UART0_CTSB"),
|
||||
PINCTRL_PIN(49, "ISH_GP_4"),
|
||||
PINCTRL_PIN(50, "ISH_GP_5"),
|
||||
PINCTRL_PIN(51, "I2S_MCLK1_OUT"),
|
||||
PINCTRL_PIN(52, "GSPI2_CLK_LOOPBK"),
|
||||
/* GPP_U */
|
||||
PINCTRL_PIN(53, "UART3_RXD"),
|
||||
PINCTRL_PIN(54, "UART3_TXD"),
|
||||
PINCTRL_PIN(55, "UART3_RTSB"),
|
||||
PINCTRL_PIN(56, "UART3_CTSB"),
|
||||
PINCTRL_PIN(57, "GSPI3_CS0B"),
|
||||
PINCTRL_PIN(58, "GSPI3_CLK"),
|
||||
PINCTRL_PIN(59, "GSPI3_MISO"),
|
||||
PINCTRL_PIN(60, "GSPI3_MOSI"),
|
||||
PINCTRL_PIN(61, "GSPI4_CS0B"),
|
||||
PINCTRL_PIN(62, "GSPI4_CLK"),
|
||||
PINCTRL_PIN(63, "GSPI4_MISO"),
|
||||
PINCTRL_PIN(64, "GSPI4_MOSI"),
|
||||
PINCTRL_PIN(65, "GSPI5_CS0B"),
|
||||
PINCTRL_PIN(66, "GSPI5_CLK"),
|
||||
PINCTRL_PIN(67, "GSPI5_MISO"),
|
||||
PINCTRL_PIN(68, "GSPI5_MOSI"),
|
||||
PINCTRL_PIN(69, "GSPI6_CS0B"),
|
||||
PINCTRL_PIN(70, "GSPI6_CLK"),
|
||||
PINCTRL_PIN(71, "GSPI6_MISO"),
|
||||
PINCTRL_PIN(72, "GSPI6_MOSI"),
|
||||
PINCTRL_PIN(73, "GSPI3_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(74, "GSPI4_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(75, "GSPI5_CLK_LOOPBK"),
|
||||
PINCTRL_PIN(76, "GSPI6_CLK_LOOPBK"),
|
||||
/* vGPIO */
|
||||
PINCTRL_PIN(77, "CNV_BTEN"),
|
||||
PINCTRL_PIN(78, "CNV_BT_HOST_WAKEB"),
|
||||
PINCTRL_PIN(79, "CNV_BT_IF_SELECT"),
|
||||
PINCTRL_PIN(80, "vCNV_BT_UART_TXD"),
|
||||
PINCTRL_PIN(81, "vCNV_BT_UART_RXD"),
|
||||
PINCTRL_PIN(82, "vCNV_BT_UART_CTS_B"),
|
||||
PINCTRL_PIN(83, "vCNV_BT_UART_RTS_B"),
|
||||
PINCTRL_PIN(84, "vCNV_MFUART1_TXD"),
|
||||
PINCTRL_PIN(85, "vCNV_MFUART1_RXD"),
|
||||
PINCTRL_PIN(86, "vCNV_MFUART1_CTS_B"),
|
||||
PINCTRL_PIN(87, "vCNV_MFUART1_RTS_B"),
|
||||
PINCTRL_PIN(88, "vUART0_TXD"),
|
||||
PINCTRL_PIN(89, "vUART0_RXD"),
|
||||
PINCTRL_PIN(90, "vUART0_CTS_B"),
|
||||
PINCTRL_PIN(91, "vUART0_RTS_B"),
|
||||
PINCTRL_PIN(92, "vISH_UART0_TXD"),
|
||||
PINCTRL_PIN(93, "vISH_UART0_RXD"),
|
||||
PINCTRL_PIN(94, "vISH_UART0_CTS_B"),
|
||||
PINCTRL_PIN(95, "vISH_UART0_RTS_B"),
|
||||
PINCTRL_PIN(96, "vCNV_BT_I2S_BCLK"),
|
||||
PINCTRL_PIN(97, "vCNV_BT_I2S_WS_SYNC"),
|
||||
PINCTRL_PIN(98, "vCNV_BT_I2S_SDO"),
|
||||
PINCTRL_PIN(99, "vCNV_BT_I2S_SDI"),
|
||||
PINCTRL_PIN(100, "vI2S2_SCLK"),
|
||||
PINCTRL_PIN(101, "vI2S2_SFRM"),
|
||||
PINCTRL_PIN(102, "vI2S2_TXD"),
|
||||
PINCTRL_PIN(103, "vI2S2_RXD"),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup tgllp_community1_gpps[] = {
|
||||
TGL_GPP(0, 0, 7), /* GPP_S */
|
||||
TGL_GPP(1, 8, 31), /* GPP_H */
|
||||
TGL_GPP(2, 32, 52), /* GPP_D */
|
||||
TGL_GPP(3, 53, 76), /* GPP_U */
|
||||
TGL_GPP(4, 77, 103), /* vGPIO */
|
||||
};
|
||||
|
||||
static const struct intel_community tgllp_community1[] = {
|
||||
TGL_COMMUNITY(0, 103, tgllp_community1_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data tgllp_community1_soc_data = {
|
||||
.uid = "1",
|
||||
.pins = tgllp_community1_pins,
|
||||
.npins = ARRAY_SIZE(tgllp_community1_pins),
|
||||
.communities = tgllp_community1,
|
||||
.ncommunities = ARRAY_SIZE(tgllp_community1),
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc tgllp_community4_pins[] = {
|
||||
/* GPP_C */
|
||||
PINCTRL_PIN(0, "SMBCLK"),
|
||||
PINCTRL_PIN(1, "SMBDATA"),
|
||||
PINCTRL_PIN(2, "SMBALERTB"),
|
||||
PINCTRL_PIN(3, "SML0CLK"),
|
||||
PINCTRL_PIN(4, "SML0DATA"),
|
||||
PINCTRL_PIN(5, "SML0ALERTB"),
|
||||
PINCTRL_PIN(6, "SML1CLK"),
|
||||
PINCTRL_PIN(7, "SML1DATA"),
|
||||
PINCTRL_PIN(8, "UART0_RXD"),
|
||||
PINCTRL_PIN(9, "UART0_TXD"),
|
||||
PINCTRL_PIN(10, "UART0_RTSB"),
|
||||
PINCTRL_PIN(11, "UART0_CTSB"),
|
||||
PINCTRL_PIN(12, "UART1_RXD"),
|
||||
PINCTRL_PIN(13, "UART1_TXD"),
|
||||
PINCTRL_PIN(14, "UART1_RTSB"),
|
||||
PINCTRL_PIN(15, "UART1_CTSB"),
|
||||
PINCTRL_PIN(16, "I2C0_SDA"),
|
||||
PINCTRL_PIN(17, "I2C0_SCL"),
|
||||
PINCTRL_PIN(18, "I2C1_SDA"),
|
||||
PINCTRL_PIN(19, "I2C1_SCL"),
|
||||
PINCTRL_PIN(20, "UART2_RXD"),
|
||||
PINCTRL_PIN(21, "UART2_TXD"),
|
||||
PINCTRL_PIN(22, "UART2_RTSB"),
|
||||
PINCTRL_PIN(23, "UART2_CTSB"),
|
||||
/* GPP_F */
|
||||
PINCTRL_PIN(24, "CNV_BRI_DT"),
|
||||
PINCTRL_PIN(25, "CNV_BRI_RSP"),
|
||||
PINCTRL_PIN(26, "CNV_RGI_DT"),
|
||||
PINCTRL_PIN(27, "CNV_RGI_RSP"),
|
||||
PINCTRL_PIN(28, "CNV_RF_RESET_B"),
|
||||
PINCTRL_PIN(29, "GPPC_F_5"),
|
||||
PINCTRL_PIN(30, "CNV_PA_BLANKING"),
|
||||
PINCTRL_PIN(31, "GPPC_F_7"),
|
||||
PINCTRL_PIN(32, "I2S_MCLK2_INOUT"),
|
||||
PINCTRL_PIN(33, "BOOTMPC"),
|
||||
PINCTRL_PIN(34, "GPPC_F_10"),
|
||||
PINCTRL_PIN(35, "GPPC_F_11"),
|
||||
PINCTRL_PIN(36, "GSXDOUT"),
|
||||
PINCTRL_PIN(37, "GSXSLOAD"),
|
||||
PINCTRL_PIN(38, "GSXDIN"),
|
||||
PINCTRL_PIN(39, "GSXSRESETB"),
|
||||
PINCTRL_PIN(40, "GSXCLK"),
|
||||
PINCTRL_PIN(41, "GMII_MDC"),
|
||||
PINCTRL_PIN(42, "GMII_MDIO"),
|
||||
PINCTRL_PIN(43, "SRCCLKREQB_6"),
|
||||
PINCTRL_PIN(44, "EXT_PWR_GATEB"),
|
||||
PINCTRL_PIN(45, "EXT_PWR_GATE2B"),
|
||||
PINCTRL_PIN(46, "VNN_CTRL"),
|
||||
PINCTRL_PIN(47, "V1P05_CTRL"),
|
||||
PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"),
|
||||
/* HVCMOS */
|
||||
PINCTRL_PIN(49, "L_BKLTEN"),
|
||||
PINCTRL_PIN(50, "L_BKLTCTL"),
|
||||
PINCTRL_PIN(51, "L_VDDEN"),
|
||||
PINCTRL_PIN(52, "SYS_PWROK"),
|
||||
PINCTRL_PIN(53, "SYS_RESETB"),
|
||||
PINCTRL_PIN(54, "MLK_RSTB"),
|
||||
/* GPP_E */
|
||||
PINCTRL_PIN(55, "SATAXPCIE_0"),
|
||||
PINCTRL_PIN(56, "SPI1_IO_2"),
|
||||
PINCTRL_PIN(57, "SPI1_IO_3"),
|
||||
PINCTRL_PIN(58, "CPU_GP_0"),
|
||||
PINCTRL_PIN(59, "SATA_DEVSLP_0"),
|
||||
PINCTRL_PIN(60, "SATA_DEVSLP_1"),
|
||||
PINCTRL_PIN(61, "GPPC_E_6"),
|
||||
PINCTRL_PIN(62, "CPU_GP_1"),
|
||||
PINCTRL_PIN(63, "SPI1_CS1B"),
|
||||
PINCTRL_PIN(64, "USB2_OCB_0"),
|
||||
PINCTRL_PIN(65, "SPI1_CSB"),
|
||||
PINCTRL_PIN(66, "SPI1_CLK"),
|
||||
PINCTRL_PIN(67, "SPI1_MISO_IO_1"),
|
||||
PINCTRL_PIN(68, "SPI1_MOSI_IO_0"),
|
||||
PINCTRL_PIN(69, "DDSP_HPD_A"),
|
||||
PINCTRL_PIN(70, "ISH_GP_6"),
|
||||
PINCTRL_PIN(71, "ISH_GP_7"),
|
||||
PINCTRL_PIN(72, "GPPC_E_17"),
|
||||
PINCTRL_PIN(73, "DDP1_CTRLCLK"),
|
||||
PINCTRL_PIN(74, "DDP1_CTRLDATA"),
|
||||
PINCTRL_PIN(75, "DDP2_CTRLCLK"),
|
||||
PINCTRL_PIN(76, "DDP2_CTRLDATA"),
|
||||
PINCTRL_PIN(77, "DDPA_CTRLCLK"),
|
||||
PINCTRL_PIN(78, "DDPA_CTRLDATA"),
|
||||
PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"),
|
||||
/* JTAG */
|
||||
PINCTRL_PIN(80, "JTAG_TDO"),
|
||||
PINCTRL_PIN(81, "JTAGX"),
|
||||
PINCTRL_PIN(82, "PRDYB"),
|
||||
PINCTRL_PIN(83, "PREQB"),
|
||||
PINCTRL_PIN(84, "CPU_TRSTB"),
|
||||
PINCTRL_PIN(85, "JTAG_TDI"),
|
||||
PINCTRL_PIN(86, "JTAG_TMS"),
|
||||
PINCTRL_PIN(87, "JTAG_TCK"),
|
||||
PINCTRL_PIN(88, "DBG_PMODE"),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup tgllp_community4_gpps[] = {
|
||||
TGL_GPP(0, 0, 23), /* GPP_C */
|
||||
TGL_GPP(1, 24, 48), /* GPP_F */
|
||||
TGL_GPP(2, 49, 54), /* HVCMOS */
|
||||
TGL_GPP(3, 55, 79), /* GPP_E */
|
||||
TGL_GPP(4, 80, 88), /* JTAG */
|
||||
};
|
||||
|
||||
static const struct intel_community tgllp_community4[] = {
|
||||
TGL_COMMUNITY(0, 88, tgllp_community4_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data tgllp_community4_soc_data = {
|
||||
.uid = "4",
|
||||
.pins = tgllp_community4_pins,
|
||||
.npins = ARRAY_SIZE(tgllp_community4_pins),
|
||||
.communities = tgllp_community4,
|
||||
.ncommunities = ARRAY_SIZE(tgllp_community4),
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc tgllp_community5_pins[] = {
|
||||
/* GPP_R */
|
||||
PINCTRL_PIN(0, "HDA_BCLK"),
|
||||
PINCTRL_PIN(1, "HDA_SYNC"),
|
||||
PINCTRL_PIN(2, "HDA_SDO"),
|
||||
PINCTRL_PIN(3, "HDA_SDI_0"),
|
||||
PINCTRL_PIN(4, "HDA_RSTB"),
|
||||
PINCTRL_PIN(5, "HDA_SDI_1"),
|
||||
PINCTRL_PIN(6, "GPP_R_6"),
|
||||
PINCTRL_PIN(7, "GPP_R_7"),
|
||||
/* SPI */
|
||||
PINCTRL_PIN(8, "SPI0_IO_2"),
|
||||
PINCTRL_PIN(9, "SPI0_IO_3"),
|
||||
PINCTRL_PIN(10, "SPI0_MOSI_IO_0"),
|
||||
PINCTRL_PIN(11, "SPI0_MISO_IO_1"),
|
||||
PINCTRL_PIN(12, "SPI0_TPM_CSB"),
|
||||
PINCTRL_PIN(13, "SPI0_FLASH_0_CSB"),
|
||||
PINCTRL_PIN(14, "SPI0_FLASH_1_CSB"),
|
||||
PINCTRL_PIN(15, "SPI0_CLK"),
|
||||
PINCTRL_PIN(16, "SPI0_CLK_LOOPBK"),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup tgllp_community5_gpps[] = {
|
||||
TGL_GPP(0, 0, 7), /* GPP_R */
|
||||
TGL_GPP(1, 8, 16), /* SPI */
|
||||
};
|
||||
|
||||
static const struct intel_community tgllp_community5[] = {
|
||||
TGL_COMMUNITY(0, 16, tgllp_community5_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data tgllp_community5_soc_data = {
|
||||
.uid = "5",
|
||||
.pins = tgllp_community5_pins,
|
||||
.npins = ARRAY_SIZE(tgllp_community5_pins),
|
||||
.communities = tgllp_community5,
|
||||
.ncommunities = ARRAY_SIZE(tgllp_community5),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data *tgllp_soc_data_array[] = {
|
||||
&tgllp_community0_soc_data,
|
||||
&tgllp_community1_soc_data,
|
||||
&tgllp_community4_soc_data,
|
||||
&tgllp_community5_soc_data,
|
||||
NULL
|
||||
};
|
||||
|
||||
static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
|
||||
{ "INT34C5", (kernel_ulong_t)tgllp_soc_data_array },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
|
||||
|
||||
static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
|
||||
|
||||
static struct platform_driver tgl_pinctrl_driver = {
|
||||
.probe = intel_pinctrl_probe_by_uid,
|
||||
.driver = {
|
||||
.name = "tigerlake-pinctrl",
|
||||
.acpi_match_table = tgl_pinctrl_acpi_match,
|
||||
.pm = &tgl_pinctrl_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(tgl_pinctrl_driver);
|
||||
|
||||
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|
||||
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
|
||||
MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user