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drm/i915/adl_s: Add ADL-S platform info and PCI ids
- Add the initial platform information for Alderlake-S. - Specify ppgtt_size value - Add dma_mask_size - Add ADLS REVIDs - HW tracking(Selective Update Tracking Enable) has been removed from ADLS. Disable PSR2 till we enable software/ manual tracking. v2: - Add support for different ADLS SOC steppings to select correct GT/DISP stepping based on Bspec 53655 based on feedback from Matt Roper.(aswarup) v3: - Make display/gt steppings info generic for reuse with TGL and ADLS. - Modify the macros to reuse tgl_revids_get() - Add HTI support to adls device info.(mdroper) v4: - Rebase on TGL patch for applying WAs based on stepping info from Matt Roper's feedback.(aswarup) v5: - Replace macros with PCI IDs in revid to stepping table. v6: remove stray adls_revids (Lucas) Bspec: 53597 Bspec: 53648 Bspec: 53655 Bspec: 48028 Bspec: 53650 BSpec: 50422 Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210119192931.1116500-2-lucas.demarchi@intel.com
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@ -84,6 +84,14 @@ const struct i915_rev_steppings tgl_revid_step_tbl[] = {
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[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
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};
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const struct i915_rev_steppings adls_revid_step_tbl[] = {
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[0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
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[0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
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[0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
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[0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
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[0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
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};
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static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
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{
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wal->name = name;
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@ -1417,6 +1417,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
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#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
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#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
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#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
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#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
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#define IS_BDW_ULT(dev_priv) \
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@ -1560,6 +1561,7 @@ extern const struct i915_rev_steppings kbl_revids[];
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enum {
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STEP_A0,
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STEP_A2,
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STEP_B0,
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STEP_B1,
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STEP_C0,
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@ -1568,9 +1570,11 @@ enum {
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#define TGL_UY_REVID_STEP_TBL_SIZE 4
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#define TGL_REVID_STEP_TBL_SIZE 2
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#define ADLS_REVID_STEP_TBL_SIZE 13
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extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
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extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
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extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];
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static inline const struct i915_rev_steppings *
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tgl_stepping_get(struct drm_i915_private *dev_priv)
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@ -1579,7 +1583,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
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u8 size;
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const struct i915_rev_steppings *revid_step_tbl;
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if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
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if (IS_ALDERLAKE_S(dev_priv)) {
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revid_step_tbl = adls_revid_step_tbl;
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size = ARRAY_SIZE(adls_revid_step_tbl);
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} else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
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revid_step_tbl = tgl_uy_revid_step_tbl;
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size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
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} else {
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@ -1621,6 +1628,22 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
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#define IS_DG1_REVID(p, since, until) \
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(IS_DG1(p) && IS_REVID(p, since, until))
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#define ADLS_REVID_A0 0x0
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#define ADLS_REVID_A2 0x1
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#define ADLS_REVID_B0 0x4
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#define ADLS_REVID_G0 0x8
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#define ADLS_REVID_C0 0xC /*Same as H0 ADLS SOC stepping*/
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#define IS_ADLS_DISP_STEPPING(p, since, until) \
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(IS_ALDERLAKE_S(p) && \
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tgl_stepping_get(p)->disp_stepping >= (since) && \
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tgl_stepping_get(p)->disp_stepping <= (until))
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#define IS_ADLS_GT_STEPPING(p, since, until) \
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(IS_ALDERLAKE_S(p) && \
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tgl_stepping_get(p)->gt_stepping >= (since) && \
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tgl_stepping_get(p)->gt_stepping <= (until))
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#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
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#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
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#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
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@ -923,6 +923,18 @@ static const struct intel_device_info dg1_info __maybe_unused = {
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.ppgtt_size = 47,
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};
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static const struct intel_device_info adl_s_info = {
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GEN12_FEATURES,
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PLATFORM(INTEL_ALDERLAKE_S),
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.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
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.require_force_probe = 1,
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.display.has_hti = 1,
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.display.has_psr_hw_tracking = 0,
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.platform_engine_mask =
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BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
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.dma_mask_size = 46,
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};
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#undef GEN
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#undef PLATFORM
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@ -999,6 +1011,7 @@ static const struct pci_device_id pciidlist[] = {
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INTEL_JSL_IDS(&jsl_info),
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INTEL_TGL_12_IDS(&tgl_info),
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INTEL_RKL_IDS(&rkl_info),
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INTEL_ADLS_IDS(&adl_s_info),
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{0, 0, 0}
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};
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MODULE_DEVICE_TABLE(pci, pciidlist);
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@ -66,6 +66,7 @@ static const char * const platform_names[] = {
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PLATFORM_NAME(TIGERLAKE),
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PLATFORM_NAME(ROCKETLAKE),
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PLATFORM_NAME(DG1),
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PLATFORM_NAME(ALDERLAKE_S),
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};
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#undef PLATFORM_NAME
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@ -84,6 +84,7 @@ enum intel_platform {
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INTEL_TIGERLAKE,
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INTEL_ROCKETLAKE,
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INTEL_DG1,
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INTEL_ALDERLAKE_S,
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INTEL_MAX_PLATFORMS
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};
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@ -634,4 +634,15 @@
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INTEL_VGA_DEVICE(0x4907, info), \
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INTEL_VGA_DEVICE(0x4908, info)
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/* ADL-S */
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#define INTEL_ADLS_IDS(info) \
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INTEL_VGA_DEVICE(0x4680, info), \
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INTEL_VGA_DEVICE(0x4681, info), \
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INTEL_VGA_DEVICE(0x4682, info), \
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INTEL_VGA_DEVICE(0x4683, info), \
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INTEL_VGA_DEVICE(0x4690, info), \
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INTEL_VGA_DEVICE(0x4691, info), \
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INTEL_VGA_DEVICE(0x4692, info), \
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INTEL_VGA_DEVICE(0x4693, info)
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#endif /* _I915_PCIIDS_H */
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