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usb: musb: dsps: use musb register read/write wrappers instead
musb core already exports the register read/write wrappers, so clean up the duplication in dsps glue. Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Bin Liu
Greg Kroah-Hartman
parent
b99d3659b3
commit
086b288282
@ -51,30 +51,6 @@
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static const struct of_device_id musb_dsps_of_match[];
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/**
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* avoid using musb_readx()/musb_writex() as glue layer should not be
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* dependent on musb core layer symbols.
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*/
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static inline u8 dsps_readb(const void __iomem *addr, unsigned offset)
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{
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return __raw_readb(addr + offset);
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}
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static inline u32 dsps_readl(const void __iomem *addr, unsigned offset)
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{
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return __raw_readl(addr + offset);
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}
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static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data)
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{
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__raw_writeb(data, addr + offset);
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}
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static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data)
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{
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__raw_writel(data, addr + offset);
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}
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/**
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* DSPS musb wrapper register offset.
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* FIXME: This should be expanded to have all the wrapper registers from TI DSPS
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@ -223,8 +199,8 @@ static void dsps_musb_enable(struct musb *musb)
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((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
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coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
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dsps_writel(reg_base, wrp->epintr_set, epmask);
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dsps_writel(reg_base, wrp->coreintr_set, coremask);
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musb_writel(reg_base, wrp->epintr_set, epmask);
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musb_writel(reg_base, wrp->coreintr_set, coremask);
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/* start polling for ID change in dual-role idle mode */
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if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
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musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
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@ -244,10 +220,10 @@ static void dsps_musb_disable(struct musb *musb)
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const struct dsps_musb_wrapper *wrp = glue->wrp;
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void __iomem *reg_base = musb->ctrl_base;
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dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
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dsps_writel(reg_base, wrp->epintr_clear,
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musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
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musb_writel(reg_base, wrp->epintr_clear,
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wrp->txep_bitmap | wrp->rxep_bitmap);
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dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
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musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
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}
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static void otg_timer(unsigned long _musb)
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@ -265,14 +241,14 @@ static void otg_timer(unsigned long _musb)
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* We poll because DSPS IP's won't expose several OTG-critical
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* status change events (from the transceiver) otherwise.
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*/
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devctl = dsps_readb(mregs, MUSB_DEVCTL);
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
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usb_otg_state_string(musb->xceiv->otg->state));
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spin_lock_irqsave(&musb->lock, flags);
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switch (musb->xceiv->otg->state) {
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case OTG_STATE_A_WAIT_BCON:
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dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
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musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
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skip_session = 1;
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/* fall */
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@ -286,13 +262,13 @@ static void otg_timer(unsigned long _musb)
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MUSB_HST_MODE(musb);
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}
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if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
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dsps_writeb(mregs, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
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musb_writeb(mregs, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
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mod_timer(&glue->timer, jiffies +
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msecs_to_jiffies(wrp->poll_timeout));
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break;
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case OTG_STATE_A_WAIT_VFALL:
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
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dsps_writel(musb->ctrl_base, wrp->coreintr_set,
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musb_writel(musb->ctrl_base, wrp->coreintr_set,
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MUSB_INTR_VBUSERROR << wrp->usb_shift);
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break;
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default:
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@ -315,29 +291,29 @@ static irqreturn_t dsps_interrupt(int irq, void *hci)
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spin_lock_irqsave(&musb->lock, flags);
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/* Get endpoint interrupts */
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epintr = dsps_readl(reg_base, wrp->epintr_status);
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epintr = musb_readl(reg_base, wrp->epintr_status);
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musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
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musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
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if (epintr)
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dsps_writel(reg_base, wrp->epintr_status, epintr);
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musb_writel(reg_base, wrp->epintr_status, epintr);
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/* Get usb core interrupts */
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usbintr = dsps_readl(reg_base, wrp->coreintr_status);
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usbintr = musb_readl(reg_base, wrp->coreintr_status);
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if (!usbintr && !epintr)
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goto out;
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musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
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if (usbintr)
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dsps_writel(reg_base, wrp->coreintr_status, usbintr);
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musb_writel(reg_base, wrp->coreintr_status, usbintr);
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dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
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usbintr, epintr);
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if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
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int drvvbus = dsps_readl(reg_base, wrp->status);
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int drvvbus = musb_readl(reg_base, wrp->status);
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void __iomem *mregs = musb->mregs;
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u8 devctl = dsps_readb(mregs, MUSB_DEVCTL);
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u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
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int err;
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err = musb->int_usb & MUSB_INTR_VBUSERROR;
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@ -442,7 +418,7 @@ static int dsps_musb_init(struct musb *musb)
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musb->phy = devm_phy_get(dev->parent, "usb2-phy");
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/* Returns zero if e.g. not clocked */
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rev = dsps_readl(reg_base, wrp->revision);
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rev = musb_readl(reg_base, wrp->revision);
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if (!rev)
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return -ENODEV;
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@ -463,14 +439,14 @@ static int dsps_musb_init(struct musb *musb)
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setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
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/* Reset the musb */
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dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
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musb_writel(reg_base, wrp->control, (1 << wrp->reset));
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musb->isr = dsps_interrupt;
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/* reset the otgdisable bit, needed for host mode to work */
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val = dsps_readl(reg_base, wrp->phy_utmi);
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val = musb_readl(reg_base, wrp->phy_utmi);
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val &= ~(1 << wrp->otg_disable);
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dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
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musb_writel(musb->ctrl_base, wrp->phy_utmi, val);
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/*
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* Check whether the dsps version has babble control enabled.
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@ -478,11 +454,11 @@ static int dsps_musb_init(struct musb *musb)
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* If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
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* logic enabled.
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*/
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val = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);
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val = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
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if (val & MUSB_BABBLE_RCV_DISABLE) {
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glue->sw_babble_enabled = true;
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val |= MUSB_BABBLE_SW_SESSION_CTRL;
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dsps_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
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musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
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}
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return dsps_musb_dbg_init(musb, glue);
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@ -510,7 +486,7 @@ static int dsps_musb_set_mode(struct musb *musb, u8 mode)
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void __iomem *ctrl_base = musb->ctrl_base;
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u32 reg;
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reg = dsps_readl(ctrl_base, wrp->mode);
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reg = musb_readl(ctrl_base, wrp->mode);
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switch (mode) {
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case MUSB_HOST:
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@ -523,8 +499,8 @@ static int dsps_musb_set_mode(struct musb *musb, u8 mode)
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*/
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reg |= (1 << wrp->iddig_mux);
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dsps_writel(ctrl_base, wrp->mode, reg);
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dsps_writel(ctrl_base, wrp->phy_utmi, 0x02);
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musb_writel(ctrl_base, wrp->mode, reg);
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musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
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break;
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case MUSB_PERIPHERAL:
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reg |= (1 << wrp->iddig);
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@ -536,10 +512,10 @@ static int dsps_musb_set_mode(struct musb *musb, u8 mode)
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*/
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reg |= (1 << wrp->iddig_mux);
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dsps_writel(ctrl_base, wrp->mode, reg);
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musb_writel(ctrl_base, wrp->mode, reg);
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break;
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case MUSB_OTG:
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dsps_writel(ctrl_base, wrp->phy_utmi, 0x02);
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musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
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break;
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default:
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dev_err(glue->dev, "unsupported mode %d\n", mode);
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@ -554,7 +530,7 @@ static bool dsps_sw_babble_control(struct musb *musb)
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u8 babble_ctl;
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bool session_restart = false;
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babble_ctl = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);
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babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
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dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n",
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babble_ctl);
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/*
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@ -571,14 +547,14 @@ static bool dsps_sw_babble_control(struct musb *musb)
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* babble is due to noise, then set transmit idle (d7 bit)
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* to resume normal operation
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*/
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babble_ctl = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);
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babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
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babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE;
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dsps_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);
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musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);
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/* wait till line monitor flag cleared */
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dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
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do {
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babble_ctl = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);
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babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
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udelay(1);
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} while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--);
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@ -896,13 +872,13 @@ static int dsps_suspend(struct device *dev)
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return 0;
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mbase = musb->ctrl_base;
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glue->context.control = dsps_readl(mbase, wrp->control);
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glue->context.epintr = dsps_readl(mbase, wrp->epintr_set);
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glue->context.coreintr = dsps_readl(mbase, wrp->coreintr_set);
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glue->context.phy_utmi = dsps_readl(mbase, wrp->phy_utmi);
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glue->context.mode = dsps_readl(mbase, wrp->mode);
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glue->context.tx_mode = dsps_readl(mbase, wrp->tx_mode);
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glue->context.rx_mode = dsps_readl(mbase, wrp->rx_mode);
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glue->context.control = musb_readl(mbase, wrp->control);
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glue->context.epintr = musb_readl(mbase, wrp->epintr_set);
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glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set);
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glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi);
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glue->context.mode = musb_readl(mbase, wrp->mode);
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glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode);
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glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode);
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return 0;
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}
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@ -918,13 +894,13 @@ static int dsps_resume(struct device *dev)
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return 0;
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mbase = musb->ctrl_base;
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dsps_writel(mbase, wrp->control, glue->context.control);
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dsps_writel(mbase, wrp->epintr_set, glue->context.epintr);
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dsps_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
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dsps_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
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dsps_writel(mbase, wrp->mode, glue->context.mode);
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dsps_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
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dsps_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
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musb_writel(mbase, wrp->control, glue->context.control);
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musb_writel(mbase, wrp->epintr_set, glue->context.epintr);
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musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
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musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
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musb_writel(mbase, wrp->mode, glue->context.mode);
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musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
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musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
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if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
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musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
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mod_timer(&glue->timer, jiffies +
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