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ARM: at91: remove unused headers
Following the switch to multiplatform, uncompress.h is not used anymore. Remove it. at91_dbgu.h is also not used anymore Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Alexandre Belloni
Nicolas Ferre
parent
f6d1c094f7
commit
0794261104
@ -1,63 +0,0 @@
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/*
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* arch/arm/mach-at91/include/mach/at91_dbgu.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Debug Unit (DBGU) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_DBGU_H
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#define AT91_DBGU_H
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#define AT91_DBGU_CR (0x00) /* Control Register */
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#define AT91_DBGU_MR (0x04) /* Mode Register */
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#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
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#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
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#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
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#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
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#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
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#define AT91_DBGU_SR (0x14) /* Status Register */
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#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
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#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
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#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
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#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
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#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
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#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
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#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
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/*
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* Some AT91 parts that don't have full DEBUG units still support the ID
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* and extensions register.
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*/
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#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
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#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
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#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
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#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
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#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
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#define AT91_CIDR_SRAMSIZ_1K (1 << 16)
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#define AT91_CIDR_SRAMSIZ_2K (2 << 16)
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#define AT91_CIDR_SRAMSIZ_112K (4 << 16)
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#define AT91_CIDR_SRAMSIZ_4K (5 << 16)
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#define AT91_CIDR_SRAMSIZ_80K (6 << 16)
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#define AT91_CIDR_SRAMSIZ_160K (7 << 16)
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#define AT91_CIDR_SRAMSIZ_8K (8 << 16)
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#define AT91_CIDR_SRAMSIZ_16K (9 << 16)
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#define AT91_CIDR_SRAMSIZ_32K (10 << 16)
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#define AT91_CIDR_SRAMSIZ_64K (11 << 16)
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#define AT91_CIDR_SRAMSIZ_128K (12 << 16)
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#define AT91_CIDR_SRAMSIZ_256K (13 << 16)
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#define AT91_CIDR_SRAMSIZ_96K (14 << 16)
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#define AT91_CIDR_SRAMSIZ_512K (15 << 16)
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#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
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#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
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#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
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#endif
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@ -1,218 +0,0 @@
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/*
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* arch/arm/mach-at91/include/mach/uncompress.h
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*
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* Copyright (C) 2003 SAN People
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* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_UNCOMPRESS_H
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#define __ASM_ARCH_UNCOMPRESS_H
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#include <linux/io.h>
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#include <linux/atmel_serial.h>
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#include <mach/hardware.h>
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#include <mach/at91_dbgu.h>
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#include <mach/cpu.h>
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void __iomem *at91_uart;
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static const u32 uarts_rm9200[] = {
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AT91_BASE_DBGU0,
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AT91RM9200_BASE_US0,
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AT91RM9200_BASE_US1,
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AT91RM9200_BASE_US2,
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AT91RM9200_BASE_US3,
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0,
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};
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static const u32 uarts_sam9260[] = {
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AT91_BASE_DBGU0,
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AT91SAM9260_BASE_US0,
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AT91SAM9260_BASE_US1,
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AT91SAM9260_BASE_US2,
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AT91SAM9260_BASE_US3,
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AT91SAM9260_BASE_US4,
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AT91SAM9260_BASE_US5,
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0,
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};
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static const u32 uarts_sam9261[] = {
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AT91_BASE_DBGU0,
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AT91SAM9261_BASE_US0,
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AT91SAM9261_BASE_US1,
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AT91SAM9261_BASE_US2,
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0,
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};
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static const u32 uarts_sam9263[] = {
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AT91_BASE_DBGU1,
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AT91SAM9263_BASE_US0,
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AT91SAM9263_BASE_US1,
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AT91SAM9263_BASE_US2,
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0,
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};
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static const u32 uarts_sam9g45[] = {
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AT91_BASE_DBGU1,
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AT91SAM9G45_BASE_US0,
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AT91SAM9G45_BASE_US1,
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AT91SAM9G45_BASE_US2,
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AT91SAM9G45_BASE_US3,
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0,
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};
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static const u32 uarts_sam9rl[] = {
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AT91_BASE_DBGU0,
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AT91SAM9RL_BASE_US0,
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AT91SAM9RL_BASE_US1,
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AT91SAM9RL_BASE_US2,
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AT91SAM9RL_BASE_US3,
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0,
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};
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static const u32 uarts_sam9x5[] = {
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AT91_BASE_DBGU0,
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AT91SAM9X5_BASE_USART0,
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AT91SAM9X5_BASE_USART1,
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AT91SAM9X5_BASE_USART2,
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0,
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};
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static const u32 uarts_sama5d3[] = {
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AT91_BASE_DBGU1,
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SAMA5D3_BASE_USART0,
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SAMA5D3_BASE_USART1,
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SAMA5D3_BASE_USART2,
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SAMA5D3_BASE_USART3,
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0,
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};
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static const u32 uarts_sama5d4[] = {
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AT91_BASE_DBGU2,
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SAMA5D4_BASE_USART3,
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0,
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};
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static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
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{
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u32 cidr, socid;
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cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
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socid = cidr & ~AT91_CIDR_VERSION;
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switch (socid) {
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case ARCH_ID_AT91RM9200:
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return uarts_rm9200;
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case ARCH_ID_AT91SAM9G20:
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case ARCH_ID_AT91SAM9260:
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return uarts_sam9260;
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case ARCH_ID_AT91SAM9261:
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return uarts_sam9261;
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case ARCH_ID_AT91SAM9263:
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return uarts_sam9263;
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case ARCH_ID_AT91SAM9G45:
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return uarts_sam9g45;
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case ARCH_ID_AT91SAM9RL64:
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return uarts_sam9rl;
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case ARCH_ID_AT91SAM9N12:
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case ARCH_ID_AT91SAM9X5:
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return uarts_sam9x5;
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case ARCH_ID_SAMA5:
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cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
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if (cidr & ARCH_EXID_SAMA5D3)
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return uarts_sama5d3;
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else if (cidr & ARCH_EXID_SAMA5D4)
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return uarts_sama5d4;
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break;
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}
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/* at91sam9g10 */
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if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
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return uarts_sam9261;
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}
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/* at91sam9xe */
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else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
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return uarts_sam9260;
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}
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return NULL;
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}
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static inline void arch_decomp_setup(void)
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{
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int i = 0;
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const u32* usarts;
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usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
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if (!usarts)
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usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
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if (!usarts)
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usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
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if (!usarts) {
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at91_uart = NULL;
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return;
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}
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do {
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/* physical address */
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at91_uart = (void __iomem *)usarts[i];
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if (__raw_readl(at91_uart + ATMEL_US_BRGR))
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return;
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i++;
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} while (usarts[i]);
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at91_uart = NULL;
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}
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/*
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* The following code assumes the serial port has already been
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* initialized by the bootloader. If you didn't setup a port in
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* your bootloader then nothing will appear (which might be desired).
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*
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* This does not append a newline
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*/
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static void putc(int c)
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{
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if (!at91_uart)
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return;
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while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
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barrier();
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__raw_writel(c, at91_uart + ATMEL_US_THR);
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}
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static inline void flush(void)
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{
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if (!at91_uart)
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return;
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/* wait for transmission to complete */
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while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
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barrier();
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}
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#endif
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