mirror of
https://github.com/torvalds/linux.git
synced 2024-10-28 07:41:44 +00:00
Merge branches 'cma', 'cxgb3', 'ipath', 'ipoib', 'mad' and 'mlx4' into for-linus
This commit is contained in:
commit
06a91a02e9
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@ -133,7 +133,7 @@ static void ack_recv(struct mad_rmpp_recv *rmpp_recv,
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msg = ib_create_send_mad(&rmpp_recv->agent->agent, recv_wc->wc->src_qp,
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msg = ib_create_send_mad(&rmpp_recv->agent->agent, recv_wc->wc->src_qp,
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recv_wc->wc->pkey_index, 1, hdr_len,
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recv_wc->wc->pkey_index, 1, hdr_len,
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0, GFP_KERNEL);
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0, GFP_KERNEL);
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if (!msg)
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if (IS_ERR(msg))
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return;
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return;
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format_ack(msg, (struct ib_rmpp_mad *) recv_wc->recv_buf.mad, rmpp_recv);
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format_ack(msg, (struct ib_rmpp_mad *) recv_wc->recv_buf.mad, rmpp_recv);
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@ -725,9 +725,9 @@ static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
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V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
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V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
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BUG_ON(page_size >= 28);
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BUG_ON(page_size >= 28);
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tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
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tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
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F_TPT_MW_BIND_ENABLE |
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((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) |
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V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
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V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
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V_TPT_PAGE_SIZE(page_size));
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V_TPT_PAGE_SIZE(page_size));
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tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
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tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
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cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
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cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
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tpt.len = cpu_to_be32(len);
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tpt.len = cpu_to_be32(len);
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@ -1187,28 +1187,6 @@ static ssize_t show_rev(struct device *dev, struct device_attribute *attr,
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return sprintf(buf, "%d\n", iwch_dev->rdev.t3cdev_p->type);
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return sprintf(buf, "%d\n", iwch_dev->rdev.t3cdev_p->type);
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}
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}
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static int fw_supports_fastreg(struct iwch_dev *iwch_dev)
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{
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struct ethtool_drvinfo info;
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struct net_device *lldev = iwch_dev->rdev.t3cdev_p->lldev;
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char *cp, *next;
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unsigned fw_maj, fw_min;
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rtnl_lock();
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lldev->ethtool_ops->get_drvinfo(lldev, &info);
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rtnl_unlock();
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next = info.fw_version+1;
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cp = strsep(&next, ".");
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sscanf(cp, "%i", &fw_maj);
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cp = strsep(&next, ".");
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sscanf(cp, "%i", &fw_min);
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PDBG("%s maj %u min %u\n", __func__, fw_maj, fw_min);
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return fw_maj > 6 || (fw_maj == 6 && fw_min > 0);
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}
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static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, char *buf)
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static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, char *buf)
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{
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{
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struct iwch_dev *iwch_dev = container_of(dev, struct iwch_dev,
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struct iwch_dev *iwch_dev = container_of(dev, struct iwch_dev,
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@ -1325,12 +1303,12 @@ int iwch_register_device(struct iwch_dev *dev)
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memset(&dev->ibdev.node_guid, 0, sizeof(dev->ibdev.node_guid));
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memset(&dev->ibdev.node_guid, 0, sizeof(dev->ibdev.node_guid));
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memcpy(&dev->ibdev.node_guid, dev->rdev.t3cdev_p->lldev->dev_addr, 6);
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memcpy(&dev->ibdev.node_guid, dev->rdev.t3cdev_p->lldev->dev_addr, 6);
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dev->ibdev.owner = THIS_MODULE;
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dev->ibdev.owner = THIS_MODULE;
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dev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY | IB_DEVICE_MEM_WINDOW;
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dev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY |
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IB_DEVICE_MEM_WINDOW |
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IB_DEVICE_MEM_MGT_EXTENSIONS;
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/* cxgb3 supports STag 0. */
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/* cxgb3 supports STag 0. */
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dev->ibdev.local_dma_lkey = 0;
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dev->ibdev.local_dma_lkey = 0;
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if (fw_supports_fastreg(dev))
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dev->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
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dev->ibdev.uverbs_cmd_mask =
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dev->ibdev.uverbs_cmd_mask =
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(1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
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(1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
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@ -293,9 +293,16 @@ static inline u32 iwch_ib_to_tpt_access(int acc)
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return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) |
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return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) |
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(acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0) |
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(acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0) |
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(acc & IB_ACCESS_LOCAL_WRITE ? TPT_LOCAL_WRITE : 0) |
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(acc & IB_ACCESS_LOCAL_WRITE ? TPT_LOCAL_WRITE : 0) |
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(acc & IB_ACCESS_MW_BIND ? TPT_MW_BIND : 0) |
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TPT_LOCAL_READ;
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TPT_LOCAL_READ;
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}
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}
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static inline u32 iwch_ib_to_tpt_bind_access(int acc)
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{
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return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) |
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(acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0);
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}
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enum iwch_mmid_state {
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enum iwch_mmid_state {
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IWCH_STAG_STATE_VALID,
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IWCH_STAG_STATE_VALID,
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IWCH_STAG_STATE_INVALID
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IWCH_STAG_STATE_INVALID
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@ -565,7 +565,7 @@ int iwch_bind_mw(struct ib_qp *qp,
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wqe->bind.type = TPT_VATO;
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wqe->bind.type = TPT_VATO;
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/* TBD: check perms */
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/* TBD: check perms */
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wqe->bind.perms = iwch_ib_to_tpt_access(mw_bind->mw_access_flags);
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wqe->bind.perms = iwch_ib_to_tpt_bind_access(mw_bind->mw_access_flags);
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wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey);
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wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey);
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wqe->bind.mw_stag = cpu_to_be32(mw->rkey);
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wqe->bind.mw_stag = cpu_to_be32(mw->rkey);
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wqe->bind.mw_len = cpu_to_be32(mw_bind->length);
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wqe->bind.mw_len = cpu_to_be32(mw_bind->length);
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@ -879,20 +879,13 @@ static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
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(qhp->attr.mpa_attr.xmit_marker_enabled << 1) |
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(qhp->attr.mpa_attr.xmit_marker_enabled << 1) |
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(qhp->attr.mpa_attr.crc_enabled << 2);
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(qhp->attr.mpa_attr.crc_enabled << 2);
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/*
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init_attr.qpcaps = uP_RI_QP_RDMA_READ_ENABLE |
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* XXX - The IWCM doesn't quite handle getting these
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uP_RI_QP_RDMA_WRITE_ENABLE |
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* attrs set before going into RTS. For now, just turn
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uP_RI_QP_BIND_ENABLE;
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* them on always...
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if (!qhp->ibqp.uobject)
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*/
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init_attr.qpcaps |= uP_RI_QP_STAG0_ENABLE |
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#if 0
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uP_RI_QP_FAST_REGISTER_ENABLE;
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init_attr.qpcaps = qhp->attr.enableRdmaRead |
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(qhp->attr.enableRdmaWrite << 1) |
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(qhp->attr.enableBind << 2) |
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(qhp->attr.enable_stag0_fastreg << 3) |
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(qhp->attr.enable_stag0_fastreg << 4);
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#else
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init_attr.qpcaps = 0x1f;
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#endif
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init_attr.tcp_emss = qhp->ep->emss;
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init_attr.tcp_emss = qhp->ep->emss;
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init_attr.ord = qhp->attr.max_ord;
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init_attr.ord = qhp->attr.max_ord;
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init_attr.ird = qhp->attr.max_ird;
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init_attr.ird = qhp->attr.max_ird;
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@ -900,8 +893,6 @@ static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
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init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
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init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
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init_attr.rqe_count = iwch_rqes_posted(qhp);
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init_attr.rqe_count = iwch_rqes_posted(qhp);
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init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
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init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
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if (!qhp->ibqp.uobject)
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init_attr.flags |= PRIV_QP;
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if (peer2peer) {
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if (peer2peer) {
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init_attr.rtr_type = RTR_READ;
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init_attr.rtr_type = RTR_READ;
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if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
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if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
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@ -1259,7 +1259,7 @@ reloop:
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*/
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*/
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ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
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ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
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" %x, len %x hdrq+%x rhf: %Lx\n",
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" %x, len %x hdrq+%x rhf: %Lx\n",
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etail, tlen, l,
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etail, tlen, l, (unsigned long long)
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le64_to_cpu(*(__le64 *) rhf_addr));
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le64_to_cpu(*(__le64 *) rhf_addr));
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if (ipath_debug & __IPATH_ERRPKTDBG) {
|
if (ipath_debug & __IPATH_ERRPKTDBG) {
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u32 j, *d, dw = rsize-2;
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u32 j, *d, dw = rsize-2;
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@ -1457,7 +1457,8 @@ static void ipath_reset_availshadow(struct ipath_devdata *dd)
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0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */
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0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */
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if (oldval != dd->ipath_pioavailshadow[i])
|
if (oldval != dd->ipath_pioavailshadow[i])
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ipath_dbg("shadow[%d] was %Lx, now %lx\n",
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ipath_dbg("shadow[%d] was %Lx, now %lx\n",
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i, oldval, dd->ipath_pioavailshadow[i]);
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i, (unsigned long long) oldval,
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dd->ipath_pioavailshadow[i]);
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}
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}
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spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
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spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
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}
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}
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||||||
|
|
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@ -1032,7 +1032,7 @@ static int ipath_7220_bringup_serdes(struct ipath_devdata *dd)
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ipath_cdbg(VERBOSE, "done: xgxs=%llx from %llx\n",
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ipath_cdbg(VERBOSE, "done: xgxs=%llx from %llx\n",
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||||||
(unsigned long long)
|
(unsigned long long)
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||||||
ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig),
|
ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig),
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prev_val);
|
(unsigned long long) prev_val);
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||||||
|
|
||||||
guid = be64_to_cpu(dd->ipath_guid);
|
guid = be64_to_cpu(dd->ipath_guid);
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|
||||||
|
@ -1042,7 +1042,8 @@ static int ipath_7220_bringup_serdes(struct ipath_devdata *dd)
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ipath_dbg("No GUID for heartbeat, faking %llx\n",
|
ipath_dbg("No GUID for heartbeat, faking %llx\n",
|
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(unsigned long long)guid);
|
(unsigned long long)guid);
|
||||||
} else
|
} else
|
||||||
ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n", guid);
|
ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n",
|
||||||
|
(unsigned long long) guid);
|
||||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_hrtbt_guid, guid);
|
ipath_write_kreg(dd, dd->ipath_kregs->kr_hrtbt_guid, guid);
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
@ -2505,7 +2506,7 @@ done:
|
||||||
if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
|
if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
|
||||||
ipath_dbg("Did not get to DDR INIT (%x) after %Lu msecs\n",
|
ipath_dbg("Did not get to DDR INIT (%x) after %Lu msecs\n",
|
||||||
ipath_ib_state(dd, dd->ipath_lastibcstat),
|
ipath_ib_state(dd, dd->ipath_lastibcstat),
|
||||||
jiffies_to_msecs(jiffies)-startms);
|
(unsigned long long) jiffies_to_msecs(jiffies)-startms);
|
||||||
dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
|
dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
|
||||||
if (dd->ipath_autoneg_tries == IPATH_AUTONEG_TRIES) {
|
if (dd->ipath_autoneg_tries == IPATH_AUTONEG_TRIES) {
|
||||||
dd->ipath_flags |= IPATH_IB_AUTONEG_FAILED;
|
dd->ipath_flags |= IPATH_IB_AUTONEG_FAILED;
|
||||||
|
|
|
@ -356,9 +356,10 @@ static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
|
||||||
dd->ipath_cregs->cr_iblinkerrrecovcnt);
|
dd->ipath_cregs->cr_iblinkerrrecovcnt);
|
||||||
if (linkrecov != dd->ipath_lastlinkrecov) {
|
if (linkrecov != dd->ipath_lastlinkrecov) {
|
||||||
ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n",
|
ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n",
|
||||||
ibcs, ib_linkstate(dd, ibcs),
|
(unsigned long long) ibcs,
|
||||||
|
ib_linkstate(dd, ibcs),
|
||||||
ipath_ibcstatus_str[ltstate],
|
ipath_ibcstatus_str[ltstate],
|
||||||
linkrecov);
|
(unsigned long long) linkrecov);
|
||||||
/* and no more until active again */
|
/* and no more until active again */
|
||||||
dd->ipath_lastlinkrecov = 0;
|
dd->ipath_lastlinkrecov = 0;
|
||||||
ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
|
ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
|
||||||
|
@ -1118,9 +1119,11 @@ irqreturn_t ipath_intr(int irq, void *data)
|
||||||
if (unlikely(istat & ~dd->ipath_i_bitsextant))
|
if (unlikely(istat & ~dd->ipath_i_bitsextant))
|
||||||
ipath_dev_err(dd,
|
ipath_dev_err(dd,
|
||||||
"interrupt with unknown interrupts %Lx set\n",
|
"interrupt with unknown interrupts %Lx set\n",
|
||||||
|
(unsigned long long)
|
||||||
istat & ~dd->ipath_i_bitsextant);
|
istat & ~dd->ipath_i_bitsextant);
|
||||||
else if (istat & ~INFINIPATH_I_ERROR) /* errors do own printing */
|
else if (istat & ~INFINIPATH_I_ERROR) /* errors do own printing */
|
||||||
ipath_cdbg(VERBOSE, "intr stat=0x%Lx\n", istat);
|
ipath_cdbg(VERBOSE, "intr stat=0x%Lx\n",
|
||||||
|
(unsigned long long) istat);
|
||||||
|
|
||||||
if (istat & INFINIPATH_I_ERROR) {
|
if (istat & INFINIPATH_I_ERROR) {
|
||||||
ipath_stats.sps_errints++;
|
ipath_stats.sps_errints++;
|
||||||
|
@ -1128,7 +1131,8 @@ irqreturn_t ipath_intr(int irq, void *data)
|
||||||
dd->ipath_kregs->kr_errorstatus);
|
dd->ipath_kregs->kr_errorstatus);
|
||||||
if (!estat)
|
if (!estat)
|
||||||
dev_info(&dd->pcidev->dev, "error interrupt (%Lx), "
|
dev_info(&dd->pcidev->dev, "error interrupt (%Lx), "
|
||||||
"but no error bits set!\n", istat);
|
"but no error bits set!\n",
|
||||||
|
(unsigned long long) istat);
|
||||||
else if (estat == -1LL)
|
else if (estat == -1LL)
|
||||||
/*
|
/*
|
||||||
* should we try clearing all, or hope next read
|
* should we try clearing all, or hope next read
|
||||||
|
|
|
@ -1021,7 +1021,7 @@ static void sdma_complete(void *cookie, int status)
|
||||||
struct ipath_verbs_txreq *tx = cookie;
|
struct ipath_verbs_txreq *tx = cookie;
|
||||||
struct ipath_qp *qp = tx->qp;
|
struct ipath_qp *qp = tx->qp;
|
||||||
struct ipath_ibdev *dev = to_idev(qp->ibqp.device);
|
struct ipath_ibdev *dev = to_idev(qp->ibqp.device);
|
||||||
unsigned int flags;
|
unsigned long flags;
|
||||||
enum ib_wc_status ibs = status == IPATH_SDMA_TXREQ_S_OK ?
|
enum ib_wc_status ibs = status == IPATH_SDMA_TXREQ_S_OK ?
|
||||||
IB_WC_SUCCESS : IB_WC_WR_FLUSH_ERR;
|
IB_WC_SUCCESS : IB_WC_WR_FLUSH_ERR;
|
||||||
|
|
||||||
|
@ -1051,7 +1051,7 @@ static void sdma_complete(void *cookie, int status)
|
||||||
|
|
||||||
static void decrement_dma_busy(struct ipath_qp *qp)
|
static void decrement_dma_busy(struct ipath_qp *qp)
|
||||||
{
|
{
|
||||||
unsigned int flags;
|
unsigned long flags;
|
||||||
|
|
||||||
if (atomic_dec_and_test(&qp->s_dma_busy)) {
|
if (atomic_dec_and_test(&qp->s_dma_busy)) {
|
||||||
spin_lock_irqsave(&qp->s_lock, flags);
|
spin_lock_irqsave(&qp->s_lock, flags);
|
||||||
|
@ -1221,7 +1221,7 @@ static int ipath_verbs_send_pio(struct ipath_qp *qp,
|
||||||
unsigned flush_wc;
|
unsigned flush_wc;
|
||||||
u32 control;
|
u32 control;
|
||||||
int ret;
|
int ret;
|
||||||
unsigned int flags;
|
unsigned long flags;
|
||||||
|
|
||||||
piobuf = ipath_getpiobuf(dd, plen, NULL);
|
piobuf = ipath_getpiobuf(dd, plen, NULL);
|
||||||
if (unlikely(piobuf == NULL)) {
|
if (unlikely(piobuf == NULL)) {
|
||||||
|
|
|
@ -515,17 +515,17 @@ static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
|
||||||
wc->vendor_err = cqe->vendor_err_syndrome;
|
wc->vendor_err = cqe->vendor_err_syndrome;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mlx4_ib_ipoib_csum_ok(__be32 status, __be16 checksum)
|
static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
|
||||||
{
|
{
|
||||||
return ((status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 |
|
return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
|
||||||
MLX4_CQE_IPOIB_STATUS_IPV4F |
|
MLX4_CQE_STATUS_IPV4F |
|
||||||
MLX4_CQE_IPOIB_STATUS_IPV4OPT |
|
MLX4_CQE_STATUS_IPV4OPT |
|
||||||
MLX4_CQE_IPOIB_STATUS_IPV6 |
|
MLX4_CQE_STATUS_IPV6 |
|
||||||
MLX4_CQE_IPOIB_STATUS_IPOK)) ==
|
MLX4_CQE_STATUS_IPOK)) ==
|
||||||
cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 |
|
cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
|
||||||
MLX4_CQE_IPOIB_STATUS_IPOK)) &&
|
MLX4_CQE_STATUS_IPOK)) &&
|
||||||
(status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_UDP |
|
(status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
|
||||||
MLX4_CQE_IPOIB_STATUS_TCP)) &&
|
MLX4_CQE_STATUS_TCP)) &&
|
||||||
checksum == cpu_to_be16(0xffff);
|
checksum == cpu_to_be16(0xffff);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -582,17 +582,17 @@ repoll:
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!*cur_qp ||
|
if (!*cur_qp ||
|
||||||
(be32_to_cpu(cqe->my_qpn) & 0xffffff) != (*cur_qp)->mqp.qpn) {
|
(be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
|
||||||
/*
|
/*
|
||||||
* We do not have to take the QP table lock here,
|
* We do not have to take the QP table lock here,
|
||||||
* because CQs will be locked while QPs are removed
|
* because CQs will be locked while QPs are removed
|
||||||
* from the table.
|
* from the table.
|
||||||
*/
|
*/
|
||||||
mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
|
mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
|
||||||
be32_to_cpu(cqe->my_qpn));
|
be32_to_cpu(cqe->vlan_my_qpn));
|
||||||
if (unlikely(!mqp)) {
|
if (unlikely(!mqp)) {
|
||||||
printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n",
|
printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n",
|
||||||
cq->mcq.cqn, be32_to_cpu(cqe->my_qpn) & 0xffffff);
|
cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -692,14 +692,13 @@ repoll:
|
||||||
}
|
}
|
||||||
|
|
||||||
wc->slid = be16_to_cpu(cqe->rlid);
|
wc->slid = be16_to_cpu(cqe->rlid);
|
||||||
wc->sl = cqe->sl >> 4;
|
wc->sl = be16_to_cpu(cqe->sl_vid >> 12);
|
||||||
g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
|
g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
|
||||||
wc->src_qp = g_mlpath_rqpn & 0xffffff;
|
wc->src_qp = g_mlpath_rqpn & 0xffffff;
|
||||||
wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
|
wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
|
||||||
wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
|
wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
|
||||||
wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
|
wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
|
||||||
wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->ipoib_status,
|
wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->status, cqe->checksum);
|
||||||
cqe->checksum);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -767,7 +766,7 @@ void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
|
||||||
*/
|
*/
|
||||||
while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
|
while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
|
||||||
cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
|
cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
|
||||||
if ((be32_to_cpu(cqe->my_qpn) & 0xffffff) == qpn) {
|
if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
|
||||||
if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
|
if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
|
||||||
mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
|
mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
|
||||||
++nfreed;
|
++nfreed;
|
||||||
|
|
|
@ -902,7 +902,7 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
|
||||||
context->mtu_msgmax = (IB_MTU_4096 << 5) |
|
context->mtu_msgmax = (IB_MTU_4096 << 5) |
|
||||||
ilog2(dev->dev->caps.max_gso_sz);
|
ilog2(dev->dev->caps.max_gso_sz);
|
||||||
else
|
else
|
||||||
context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
|
context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
|
||||||
} else if (attr_mask & IB_QP_PATH_MTU) {
|
} else if (attr_mask & IB_QP_PATH_MTU) {
|
||||||
if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
|
if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
|
||||||
printk(KERN_ERR "path MTU (%u) is invalid\n",
|
printk(KERN_ERR "path MTU (%u) is invalid\n",
|
||||||
|
|
|
@ -337,7 +337,7 @@ static void ipoib_cm_init_rx_wr(struct net_device *dev,
|
||||||
sge[i].length = PAGE_SIZE;
|
sge[i].length = PAGE_SIZE;
|
||||||
|
|
||||||
wr->next = NULL;
|
wr->next = NULL;
|
||||||
wr->sg_list = priv->cm.rx_sge;
|
wr->sg_list = sge;
|
||||||
wr->num_sge = priv->cm.num_frags;
|
wr->num_sge = priv->cm.num_frags;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -39,17 +39,18 @@
|
||||||
#include <linux/mlx4/doorbell.h>
|
#include <linux/mlx4/doorbell.h>
|
||||||
|
|
||||||
struct mlx4_cqe {
|
struct mlx4_cqe {
|
||||||
__be32 my_qpn;
|
__be32 vlan_my_qpn;
|
||||||
__be32 immed_rss_invalid;
|
__be32 immed_rss_invalid;
|
||||||
__be32 g_mlpath_rqpn;
|
__be32 g_mlpath_rqpn;
|
||||||
u8 sl;
|
__be16 sl_vid;
|
||||||
u8 reserved1;
|
|
||||||
__be16 rlid;
|
__be16 rlid;
|
||||||
__be32 ipoib_status;
|
__be16 status;
|
||||||
|
u8 ipv6_ext_mask;
|
||||||
|
u8 badfcs_enc;
|
||||||
__be32 byte_cnt;
|
__be32 byte_cnt;
|
||||||
__be16 wqe_index;
|
__be16 wqe_index;
|
||||||
__be16 checksum;
|
__be16 checksum;
|
||||||
u8 reserved2[3];
|
u8 reserved[3];
|
||||||
u8 owner_sr_opcode;
|
u8 owner_sr_opcode;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -63,6 +64,11 @@ struct mlx4_err_cqe {
|
||||||
u8 owner_sr_opcode;
|
u8 owner_sr_opcode;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
|
||||||
|
MLX4_CQE_QPN_MASK = 0xffffff,
|
||||||
|
};
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
MLX4_CQE_OWNER_MASK = 0x80,
|
MLX4_CQE_OWNER_MASK = 0x80,
|
||||||
MLX4_CQE_IS_SEND_MASK = 0x40,
|
MLX4_CQE_IS_SEND_MASK = 0x40,
|
||||||
|
@ -86,13 +92,19 @@ enum {
|
||||||
};
|
};
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22,
|
MLX4_CQE_STATUS_IPV4 = 1 << 6,
|
||||||
MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23,
|
MLX4_CQE_STATUS_IPV4F = 1 << 7,
|
||||||
MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24,
|
MLX4_CQE_STATUS_IPV6 = 1 << 8,
|
||||||
MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25,
|
MLX4_CQE_STATUS_IPV4OPT = 1 << 9,
|
||||||
MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26,
|
MLX4_CQE_STATUS_TCP = 1 << 10,
|
||||||
MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27,
|
MLX4_CQE_STATUS_UDP = 1 << 11,
|
||||||
MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28,
|
MLX4_CQE_STATUS_IPOK = 1 << 12,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
MLX4_CQE_LLC = 1,
|
||||||
|
MLX4_CQE_SNAP = 1 << 1,
|
||||||
|
MLX4_CQE_BAD_FCS = 1 << 4,
|
||||||
};
|
};
|
||||||
|
|
||||||
static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
|
static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
|
||||||
|
|
Loading…
Reference in New Issue
Block a user