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perf/x86/intel: Support full width counting
Recent Intel CPUs like Haswell and IvyBridge have a new alternative MSR range for perfctrs that allows writing the full counter width. Enable this range if the hardware reports it using a new capability bit. Currently the perf code queries CPUID to get the counter width, and sign extends the counter values as needed. The traditional PERFCTR MSRs always limit to 32bit, even though the counter internally is larger (usually 48 bits on recent CPUs) When the new capability is set use the alternative range which do not have these restrictions. This lowers the overhead of perf stat slightly because it has to do less interrupts to accumulate the counter value. On Haswell it also avoids some problems with TSX aborting when the end of the counter range is reached. ( See the patch "perf/x86/intel: Avoid checkpointed counters causing excessive TSX aborts" for more details. ) Signed-off-by: Andi Kleen <ak@linux.intel.com> Reviewed-by: Stephane Eranian <eranian@google.com> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1372173153-20215-1-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -170,6 +170,9 @@
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#define MSR_KNC_EVNTSEL0 0x00000028
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#define MSR_KNC_EVNTSEL1 0x00000029
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/* Alternative perfctr range with full access. */
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#define MSR_IA32_PMC0 0x000004c1
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/* AMD64 MSRs. Not complete. See the architecture manual for a more
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complete list. */
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@ -310,6 +310,11 @@ union perf_capabilities {
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u64 pebs_arch_reg:1;
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u64 pebs_format:4;
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u64 smm_freeze:1;
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/*
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* PMU supports separate counter range for writing
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* values > 32bit.
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*/
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u64 full_width_write:1;
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};
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u64 capabilities;
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};
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@ -2340,5 +2340,12 @@ __init int intel_pmu_init(void)
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}
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}
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/* Support full width counters using alternative MSR range */
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if (x86_pmu.intel_cap.full_width_write) {
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x86_pmu.max_period = x86_pmu.cntval_mask;
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x86_pmu.perfctr = MSR_IA32_PMC0;
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pr_cont("full-width counters, ");
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}
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return 0;
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}
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