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clk: qcom: Add GDSC support for SDX55 GCC
Add GDSC support to control the power supply of power domains in SDX55 GCC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201126072844.35370-7-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -424,6 +424,7 @@ config SDM_LPASSCC_845
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config SDX_GCC_55
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tristate "SDX55 Global Clock Controller"
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select QCOM_GDSC
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help
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Support for the global clock controller on SDX55 devices.
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Say Y if you want to use peripheral devices such as UART,
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@ -17,6 +17,7 @@
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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@ -1455,6 +1456,30 @@ static struct clk_branch gcc_xo_pcie_link_clk = {
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},
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};
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static struct gdsc usb30_gdsc = {
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.gdscr = 0x0b004,
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.pd = {
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.name = "usb30_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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};
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static struct gdsc pcie_gdsc = {
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.gdscr = 0x37004,
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.pd = {
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.name = "pcie_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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};
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static struct gdsc emac_gdsc = {
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.gdscr = 0x47004,
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.pd = {
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.name = "emac_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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};
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static struct clk_regmap *gcc_sdx55_clocks[] = {
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[GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr,
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[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
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@ -1560,6 +1585,12 @@ static const struct qcom_reset_map gcc_sdx55_resets[] = {
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[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 },
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};
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static struct gdsc *gcc_sdx55_gdscs[] = {
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[USB30_GDSC] = &usb30_gdsc,
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[PCIE_GDSC] = &pcie_gdsc,
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[EMAC_GDSC] = &emac_gdsc,
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};
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static const struct regmap_config gcc_sdx55_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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@ -1574,6 +1605,8 @@ static const struct qcom_cc_desc gcc_sdx55_desc = {
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.num_clks = ARRAY_SIZE(gcc_sdx55_clocks),
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.resets = gcc_sdx55_resets,
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.num_resets = ARRAY_SIZE(gcc_sdx55_resets),
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.gdscs = gcc_sdx55_gdscs,
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.num_gdscs = ARRAY_SIZE(gcc_sdx55_gdscs),
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};
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static const struct of_device_id gcc_sdx55_match_table[] = {
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