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clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()
If the nocount bit is set the divider is bypassed and the settings for the divider count should be ignored and a divider value of 1 should be assumed. Handle this correctly in the driver recalc_rate() callback. While the driver sets up the part so that the read back dividers values yield the correct result the power-on reset settings of the part might not reflect this and hence calling e.g. clk_get_rate() without prior calls to clk_set_rate() will yield the wrong result. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -40,6 +40,10 @@
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#define MMCM_REG_FILTER1 0x4e
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#define MMCM_REG_FILTER2 0x4f
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#define MMCM_CLKOUT_NOCOUNT BIT(6)
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#define MMCM_CLK_DIV_NOCOUNT BIT(12)
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struct axi_clkgen {
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void __iomem *base;
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struct clk_hw clk_hw;
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@ -315,12 +319,27 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
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unsigned int reg;
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unsigned long long tmp;
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, ®);
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dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, ®);
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if (reg & MMCM_CLKOUT_NOCOUNT) {
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dout = 1;
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} else {
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, ®);
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dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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}
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, ®);
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d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, ®);
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m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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if (reg & MMCM_CLK_DIV_NOCOUNT)
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d = 1;
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else
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d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, ®);
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if (reg & MMCM_CLKOUT_NOCOUNT) {
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m = 1;
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} else {
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, ®);
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m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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}
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if (d == 0 || dout == 0)
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return 0;
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