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drm/i915: Fix OGLC performance regression on 945
He Shuang reported an OGLC performance regression introduced in the patch "enable memory self refresh on 9xx", In that patch, SR on 945 is disabled everytime when calling intel_mark_busy(), while too much of such operation will impact performance. Actually disable SR is necessary only when GPU and Crtc changing from idle to busy. This patch make such optimization. It fixes upstream bug http://bugs.freedesktop.org/show_bug.cgi?id=26422 Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
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@ -4060,18 +4060,17 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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return;
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if (IS_I945G(dev) || IS_I945GM(dev)) {
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u32 fw_blc_self;
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if (!dev_priv->busy) {
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if (IS_I945G(dev) || IS_I945GM(dev)) {
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u32 fw_blc_self;
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DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
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fw_blc_self = I915_READ(FW_BLC_SELF);
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fw_blc_self &= ~FW_BLC_SELF_EN;
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I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
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}
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if (!dev_priv->busy)
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DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
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fw_blc_self = I915_READ(FW_BLC_SELF);
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fw_blc_self &= ~FW_BLC_SELF_EN;
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I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
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}
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dev_priv->busy = true;
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else
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} else
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mod_timer(&dev_priv->idle_timer, jiffies +
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msecs_to_jiffies(GPU_IDLE_TIMEOUT));
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@ -4083,6 +4082,14 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
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intel_fb = to_intel_framebuffer(crtc->fb);
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if (intel_fb->obj == obj) {
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if (!intel_crtc->busy) {
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if (IS_I945G(dev) || IS_I945GM(dev)) {
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u32 fw_blc_self;
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DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
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fw_blc_self = I915_READ(FW_BLC_SELF);
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fw_blc_self &= ~FW_BLC_SELF_EN;
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I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
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}
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/* Non-busy -> busy, upclock */
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intel_increase_pllclock(crtc, true);
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intel_crtc->busy = true;
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