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drm/i915: Restrict ILK-specific eDP power hack to ILK

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This eliminates a fairly long delay when power sequencing newer
hardware

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Keith Packard 2011-09-29 16:33:01 -07:00
parent bd94315971
commit 05ce1a4961
1 changed files with 35 additions and 23 deletions
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58
drivers/gpu/drm/i915/intel_dp.c
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@ -992,10 +992,12 @@ static void ironlake_edp_panel_on (struct intel_dp *intel_dp)
pp &= ~PANEL_UNLOCK_MASK; pp &= ~PANEL_UNLOCK_MASK;
pp |= PANEL_UNLOCK_REGS; pp |= PANEL_UNLOCK_REGS;
/* ILK workaround: disable reset around power sequence */ if (IS_GEN5(dev)) {
pp &= ~PANEL_POWER_RESET; /* ILK workaround: disable reset around power sequence */
I915_WRITE(PCH_PP_CONTROL, pp); pp &= ~PANEL_POWER_RESET;
POSTING_READ(PCH_PP_CONTROL); I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
}
pp |= POWER_TARGET_ON; pp |= POWER_TARGET_ON;
I915_WRITE(PCH_PP_CONTROL, pp); I915_WRITE(PCH_PP_CONTROL, pp);
@ -1006,9 +1008,11 @@ static void ironlake_edp_panel_on (struct intel_dp *intel_dp)
DRM_ERROR("panel on wait timed out: 0x%08x\n", DRM_ERROR("panel on wait timed out: 0x%08x\n",
I915_READ(PCH_PP_STATUS)); I915_READ(PCH_PP_STATUS));
pp |= PANEL_POWER_RESET; /* restore panel reset bit */ if (IS_GEN5(dev)) {
I915_WRITE(PCH_PP_CONTROL, pp); pp |= PANEL_POWER_RESET; /* restore panel reset bit */
POSTING_READ(PCH_PP_CONTROL); I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
}
} }
static void ironlake_edp_panel_off(struct drm_encoder *encoder) static void ironlake_edp_panel_off(struct drm_encoder *encoder)
@ -1025,24 +1029,32 @@ static void ironlake_edp_panel_off(struct drm_encoder *encoder)
pp &= ~PANEL_UNLOCK_MASK; pp &= ~PANEL_UNLOCK_MASK;
pp |= PANEL_UNLOCK_REGS; pp |= PANEL_UNLOCK_REGS;
/* ILK workaround: disable reset around power sequence */ if (IS_GEN5(dev)) {
pp &= ~PANEL_POWER_RESET; /* ILK workaround: disable reset around power sequence */
I915_WRITE(PCH_PP_CONTROL, pp); pp &= ~PANEL_POWER_RESET;
POSTING_READ(PCH_PP_CONTROL); I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
}
pp &= ~POWER_TARGET_ON;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
msleep(intel_dp->panel_power_cycle_delay);
if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
DRM_ERROR("panel off wait timed out: 0x%08x\n",
I915_READ(PCH_PP_STATUS));
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
intel_dp->panel_off_jiffies = jiffies; intel_dp->panel_off_jiffies = jiffies;
if (IS_GEN5(dev)) {
pp &= ~POWER_TARGET_ON;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
pp &= ~POWER_TARGET_ON;
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
msleep(intel_dp->panel_power_cycle_delay);
if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
DRM_ERROR("panel off wait timed out: 0x%08x\n",
I915_READ(PCH_PP_STATUS));
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
I915_WRITE(PCH_PP_CONTROL, pp);
POSTING_READ(PCH_PP_CONTROL);
}
} }
static void ironlake_edp_backlight_on (struct intel_dp *intel_dp) static void ironlake_edp_backlight_on (struct intel_dp *intel_dp)