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soc: qcom: llcc: Add regmap for Broadcast_AND region
Until SM8450, there was only one broadcast region (Broadcast_OR) used to broadcast write and check for status bit 0. >From SM8450 onwards another broadcast region (Broadcast_AND) has been added which checks for status bit 1. This hasn't been updated and Broadcast_OR region was wrongly being used to check for status bit 1 all along. Hence define new regmap structure for Broadcast_AND region and initialize this regmap when HW block version is greater than 4.1, otherwise initialize as a NULL pointer for backwards compatibility. Switch from broadcast_OR to broadcast_AND region (when defined in DT) for checking status bit 1 as Broadcast_OR region checks only for bit 0. Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/9cf19928a67eaa577ae0f02de5bf86276be34ea2.1717014052.git.quic_uchalich@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -855,6 +855,7 @@ EXPORT_SYMBOL_GPL(llcc_slice_putd);
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static int llcc_update_act_ctrl(u32 sid,
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u32 act_ctrl_reg_val, u32 status)
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{
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struct regmap *regmap;
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u32 act_ctrl_reg;
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u32 act_clear_reg;
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u32 status_reg;
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@ -883,7 +884,8 @@ static int llcc_update_act_ctrl(u32 sid,
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return ret;
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if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
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ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
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regmap = drv_data->bcast_and_regmap ?: drv_data->bcast_regmap;
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ret = regmap_read_poll_timeout(regmap, status_reg,
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slice_status, (slice_status & ACT_COMPLETE),
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0, LLCC_STATUS_READ_DELAY);
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if (ret)
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@ -1318,6 +1320,18 @@ static int qcom_llcc_probe(struct platform_device *pdev)
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drv_data->version = version;
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/* Applicable only when drv_data->version >= 4.1 */
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if (drv_data->version >= LLCC_VERSION_4_1_0_0) {
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drv_data->bcast_and_regmap = qcom_llcc_init_mmio(pdev, i + 1, "llcc_broadcast_and_base");
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if (IS_ERR(drv_data->bcast_and_regmap)) {
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ret = PTR_ERR(drv_data->bcast_and_regmap);
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if (ret == -EINVAL)
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drv_data->bcast_and_regmap = NULL;
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else
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goto err;
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}
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}
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llcc_cfg = cfg->sct_data;
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sz = cfg->size;
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@ -115,7 +115,8 @@ struct llcc_edac_reg_offset {
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/**
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* struct llcc_drv_data - Data associated with the llcc driver
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* @regmaps: regmaps associated with the llcc device
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* @bcast_regmap: regmap associated with llcc broadcast offset
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* @bcast_regmap: regmap associated with llcc broadcast OR offset
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* @bcast_and_regmap: regmap associated with llcc broadcast AND offset
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* @cfg: pointer to the data structure for slice configuration
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* @edac_reg_offset: Offset of the LLCC EDAC registers
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* @lock: mutex associated with each slice
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@ -129,6 +130,7 @@ struct llcc_edac_reg_offset {
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struct llcc_drv_data {
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struct regmap **regmaps;
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struct regmap *bcast_regmap;
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struct regmap *bcast_and_regmap;
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const struct llcc_slice_config *cfg;
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const struct llcc_edac_reg_offset *edac_reg_offset;
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struct mutex lock;
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