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drm/amd/powerplay: sort the call flow on temperature ranges retrieving
This can help to maintain clear code layer. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -991,6 +991,33 @@ static int smu_sw_fini(void *handle)
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return 0;
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}
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static int smu_get_thermal_temperature_range(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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struct smu_temperature_range *range =
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&smu->thermal_range;
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int ret = 0;
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if (!smu->ppt_funcs->get_thermal_temperature_range)
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return 0;
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ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
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if (ret)
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return ret;
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adev->pm.dpm.thermal.min_temp = range->min;
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adev->pm.dpm.thermal.max_temp = range->max;
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adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
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adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
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adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
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adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
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adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
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adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
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adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
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return ret;
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}
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static int smu_smc_hw_setup(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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@ -1095,6 +1122,12 @@ static int smu_smc_hw_setup(struct smu_context *smu)
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return ret;
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}
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ret = smu_get_thermal_temperature_range(smu);
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if (ret) {
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dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
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return ret;
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}
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ret = smu_enable_thermal_alert(smu);
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if (ret) {
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dev_err(adev->dev, "Failed to enable thermal alert!\n");
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@ -1037,6 +1037,8 @@ static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
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if (!range)
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return -EINVAL;
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memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
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range->max = pptable->TedgeLimit *
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SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
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range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
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@ -146,7 +146,6 @@ struct smu_power_state {
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struct smu_state_pcie_block pcie;
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struct smu_state_display_block display;
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struct smu_state_memroy_block memory;
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struct smu_temperature_range temperatures;
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struct smu_state_software_algorithm_block software;
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struct smu_uvd_clocks uvd_clocks;
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struct smu_hw_power_state hardware;
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@ -386,6 +385,7 @@ struct smu_context
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struct smu_feature smu_feature;
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struct amd_pp_display_configuration *display_config;
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struct smu_baco_context smu_baco;
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struct smu_temperature_range thermal_range;
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void *od_settings;
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#if defined(CONFIG_DEBUG_FS)
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struct dentry *debugfs_sclk;
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@ -1864,6 +1864,8 @@ static int navi10_get_thermal_temperature_range(struct smu_context *smu,
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if (!range)
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return -EINVAL;
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memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
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range->max = pptable->TedgeLimit *
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SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
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range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
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@ -1653,6 +1653,8 @@ static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
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if (!range)
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return -EINVAL;
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memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
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range->max = pptable->TemperatureLimit[TEMP_EDGE] *
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SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
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range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
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@ -85,7 +85,6 @@
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#define smu_dpm_set_jpeg_enable(smu, enable) smu_ppt_funcs(dpm_set_jpeg_enable, 0, smu, enable)
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#define smu_set_watermarks_table(smu, tab, clock_ranges) smu_ppt_funcs(set_watermarks_table, 0, smu, tab, clock_ranges)
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#define smu_thermal_temperature_range_update(smu, range, rw) smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw)
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#define smu_get_thermal_temperature_range(smu, range) smu_ppt_funcs(get_thermal_temperature_range, 0, smu, range)
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#define smu_register_irq_handler(smu) smu_ppt_funcs(register_irq_handler, 0, smu)
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#define smu_get_dpm_ultimate_freq(smu, param, min, max) smu_ppt_funcs(get_dpm_ultimate_freq, 0, smu, param, min, max)
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#define smu_asic_set_performance_level(smu, level) smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
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@ -1088,17 +1088,10 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
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int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
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{
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int ret = 0;
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struct smu_temperature_range range;
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struct amdgpu_device *adev = smu->adev;
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memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
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ret = smu_get_thermal_temperature_range(smu, &range);
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if (ret)
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return ret;
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if (smu->smu_table.thermal_controller_type) {
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ret = smu_set_thermal_range(smu, range);
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ret = smu_set_thermal_range(smu, smu->thermal_range);
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if (ret)
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return ret;
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@ -1111,16 +1104,6 @@ int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
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return ret;
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}
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adev->pm.dpm.thermal.min_temp = range.min;
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adev->pm.dpm.thermal.max_temp = range.max;
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adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
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adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
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adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
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adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
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adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
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adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
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adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
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return ret;
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}
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