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ARM: S3C24XX: Fix configuration of gpio port sizes on S3C24XX.
Some GPIO line limits are incorrectly set which, for instance, does not allow nRTS1 (GPH11) configuration on a S3C2416 chip. Signed-off-by: José Miguel Gonçalves <jose.goncalves@inov.pt> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -1059,7 +1059,7 @@ struct samsung_gpio_chip s3c24xx_gpios[] = {
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.base = S3C2410_GPA(0),
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.owner = THIS_MODULE,
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.label = "GPIOA",
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.ngpio = 24,
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.ngpio = 27,
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.direction_input = s3c24xx_gpiolib_banka_input,
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.direction_output = s3c24xx_gpiolib_banka_output,
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},
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@ -1068,7 +1068,7 @@ struct samsung_gpio_chip s3c24xx_gpios[] = {
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.base = S3C2410_GPB(0),
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.owner = THIS_MODULE,
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.label = "GPIOB",
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.ngpio = 16,
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.ngpio = 11,
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},
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}, {
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.chip = {
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@ -1113,7 +1113,7 @@ struct samsung_gpio_chip s3c24xx_gpios[] = {
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.base = S3C2410_GPH(0),
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.owner = THIS_MODULE,
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.label = "GPIOH",
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.ngpio = 11,
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.ngpio = 15,
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},
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},
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/* GPIOS for the S3C2443 and later devices. */
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@ -23,17 +23,17 @@
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* 2410 2412 2440 2443 2416
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* 2442
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* ---- ---- ---- ---- ----
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* A 23 22 25 16 25
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* B 11 11 11 11 9
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* C 16 15 16 16 16
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* A 23 22 25 16 27
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* B 11 11 11 11 11
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* C 16 16 16 16 16
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* D 16 16 16 16 16
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* E 16 16 16 16 16
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* F 8 8 8 8 8
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* G 16 16 16 16 8
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* H 11 11 9 15 15
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* H 11 11 11 15 15
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* J -- -- 13 16 --
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* K -- -- -- -- 16
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* L -- -- -- 15 7
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* L -- -- -- 15 14
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* M -- -- -- 2 2
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*/
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