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[media] rc: img-ir: biphase enabled with workaround
Biphase decoding in the current img-ir has got a quirk, where multiple Interrupts are generated when an incomplete IR code is received by the decoder. Patch adds a work around for the quirk and enables biphase decoding. Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com> Acked-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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@ -52,6 +52,11 @@ static struct img_ir_decoder *img_ir_decoders[] = {
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#define IMG_IR_QUIRK_CODE_BROKEN 0x1 /* Decode is broken */
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#define IMG_IR_QUIRK_CODE_LEN_INCR 0x2 /* Bit length needs increment */
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/*
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* The decoder generates rapid interrupts without actually having
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* received any new data after an incomplete IR code is decoded.
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*/
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#define IMG_IR_QUIRK_CODE_IRQ 0x4
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/* functions for preprocessing timings, ensuring max is set */
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@ -542,6 +547,7 @@ static void img_ir_set_decoder(struct img_ir_priv *priv,
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*/
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spin_unlock_irq(&priv->lock);
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del_timer_sync(&hw->end_timer);
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del_timer_sync(&hw->suspend_timer);
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spin_lock_irq(&priv->lock);
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hw->stopping = false;
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@ -861,6 +867,29 @@ static void img_ir_end_timer(unsigned long arg)
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spin_unlock_irq(&priv->lock);
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}
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/*
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* Timer function to re-enable the current protocol after it had been
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* cleared when invalid interrupts were generated due to a quirk in the
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* img-ir decoder.
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*/
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static void img_ir_suspend_timer(unsigned long arg)
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{
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struct img_ir_priv *priv = (struct img_ir_priv *)arg;
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spin_lock_irq(&priv->lock);
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/*
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* Don't overwrite enabled valid/match IRQs if they have already been
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* changed by e.g. a filter change.
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*/
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if ((priv->hw.quirk_suspend_irq & IMG_IR_IRQ_EDGE) ==
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img_ir_read(priv, IMG_IR_IRQ_ENABLE))
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img_ir_write(priv, IMG_IR_IRQ_ENABLE,
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priv->hw.quirk_suspend_irq);
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/* enable */
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img_ir_write(priv, IMG_IR_CONTROL, priv->hw.reg_timings.ctrl);
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spin_unlock_irq(&priv->lock);
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}
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#ifdef CONFIG_COMMON_CLK
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static void img_ir_change_frequency(struct img_ir_priv *priv,
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struct clk_notifier_data *change)
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@ -926,15 +955,38 @@ void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status)
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if (!hw->decoder)
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return;
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ct = hw->decoder->control.code_type;
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ir_status = img_ir_read(priv, IMG_IR_STATUS);
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if (!(ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2)))
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if (!(ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2))) {
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if (!(priv->hw.ct_quirks[ct] & IMG_IR_QUIRK_CODE_IRQ) ||
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hw->stopping)
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return;
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/*
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* The below functionality is added as a work around to stop
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* multiple Interrupts generated when an incomplete IR code is
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* received by the decoder.
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* The decoder generates rapid interrupts without actually
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* having received any new data. After a single interrupt it's
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* expected to clear up, but instead multiple interrupts are
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* rapidly generated. only way to get out of this loop is to
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* reset the control register after a short delay.
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*/
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img_ir_write(priv, IMG_IR_CONTROL, 0);
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hw->quirk_suspend_irq = img_ir_read(priv, IMG_IR_IRQ_ENABLE);
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img_ir_write(priv, IMG_IR_IRQ_ENABLE,
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hw->quirk_suspend_irq & IMG_IR_IRQ_EDGE);
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/* Timer activated to re-enable the protocol. */
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mod_timer(&hw->suspend_timer,
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jiffies + msecs_to_jiffies(5));
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return;
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}
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ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2);
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img_ir_write(priv, IMG_IR_STATUS, ir_status);
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len = (ir_status & IMG_IR_RXDLEN) >> IMG_IR_RXDLEN_SHIFT;
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/* some versions report wrong length for certain code types */
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ct = hw->decoder->control.code_type;
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if (hw->ct_quirks[ct] & IMG_IR_QUIRK_CODE_LEN_INCR)
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++len;
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@ -976,7 +1028,7 @@ static void img_ir_probe_hw_caps(struct img_ir_priv *priv)
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hw->ct_quirks[IMG_IR_CODETYPE_PULSELEN]
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|= IMG_IR_QUIRK_CODE_LEN_INCR;
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hw->ct_quirks[IMG_IR_CODETYPE_BIPHASE]
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|= IMG_IR_QUIRK_CODE_BROKEN;
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|= IMG_IR_QUIRK_CODE_IRQ;
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hw->ct_quirks[IMG_IR_CODETYPE_2BITPULSEPOS]
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|= IMG_IR_QUIRK_CODE_BROKEN;
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}
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@ -995,6 +1047,8 @@ int img_ir_probe_hw(struct img_ir_priv *priv)
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/* Set up the end timer */
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setup_timer(&hw->end_timer, img_ir_end_timer, (unsigned long)priv);
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setup_timer(&hw->suspend_timer, img_ir_suspend_timer,
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(unsigned long)priv);
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/* Register a clock notifier */
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if (!IS_ERR(priv->clk)) {
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@ -218,6 +218,7 @@ enum img_ir_mode {
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* @rdev: Remote control device
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* @clk_nb: Notifier block for clock notify events.
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* @end_timer: Timer until repeat timeout.
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* @suspend_timer: Timer to re-enable protocol.
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* @decoder: Current decoder settings.
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* @enabled_protocols: Currently enabled protocols.
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* @clk_hz: Current core clock rate in Hz.
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@ -228,12 +229,14 @@ enum img_ir_mode {
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* @stopping: Indicates that decoder is being taken down and timers
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* should not be restarted.
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* @suspend_irqen: Saved IRQ enable mask over suspend.
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* @quirk_suspend_irq: Saved IRQ enable mask over quirk suspend timer.
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*/
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struct img_ir_priv_hw {
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unsigned int ct_quirks[4];
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struct rc_dev *rdev;
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struct notifier_block clk_nb;
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struct timer_list end_timer;
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struct timer_list suspend_timer;
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const struct img_ir_decoder *decoder;
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u64 enabled_protocols;
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unsigned long clk_hz;
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@ -244,6 +247,7 @@ struct img_ir_priv_hw {
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enum img_ir_mode mode;
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bool stopping;
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u32 suspend_irqen;
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u32 quirk_suspend_irq;
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};
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static inline bool img_ir_hw_enabled(struct img_ir_priv_hw *hw)
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