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drm/amdgpu: add ih ip block for navy_flounder

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navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jiansong Chen 2020-02-12 22:32:01 +08:00 committed by Alex Deucher
parent fc8f07da1f
commit 026c396b41
2 changed files with 2 additions and 0 deletions
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1
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
View File

@ -270,6 +270,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
if (ih->use_bus_addr) { if (ih->use_bus_addr) {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID: case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
ih_chicken = REG_SET_FIELD(ih_chicken, ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);

1
drivers/gpu/drm/amd/amdgpu/nv.c
View File

@ -526,6 +526,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
amdgpu_device_ip_block_add(adev, &nv_common_ip_block); amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
break; break;
default: default:
return -EINVAL; return -EINVAL;