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PCI: xilinx: Use of_pci_get_host_bridge_resources() to parse DT
Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF
DT parser.
[bhelgaas: revise changelog to show similarity to 0021d22b73
("PCI: designware: Use of_pci_get_host_bridge_resources() to parse DT")]
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
parent
92e963f50f
commit
0259882e34
@ -94,9 +94,6 @@
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/* Number of MSI IRQs */
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#define XILINX_NUM_MSI_IRQS 128
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/* Number of Memory Resources */
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#define XILINX_MAX_NUM_RESOURCES 3
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/**
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* struct xilinx_pcie_port - PCIe port information
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* @reg_base: IO Mapped Register Base
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@ -105,7 +102,6 @@
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* @root_busno: Root Bus number
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* @dev: Device pointer
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* @irq_domain: IRQ domain pointer
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* @bus_range: Bus range
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* @resources: Bus Resources
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*/
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struct xilinx_pcie_port {
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@ -658,97 +654,6 @@ static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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return bus;
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}
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/**
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* xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
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* @port: PCIe port information
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*
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* Return: '0' on success and error value on failure
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*/
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static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
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{
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struct device *dev = port->dev;
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struct device_node *node = dev->of_node;
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struct resource *mem;
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resource_size_t offset;
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struct of_pci_range_parser parser;
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struct of_pci_range range;
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struct resource_entry *win;
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int err = 0, mem_resno = 0;
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/* Get the ranges */
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if (of_pci_range_parser_init(&parser, node)) {
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dev_err(dev, "missing \"ranges\" property\n");
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return -EINVAL;
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}
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/* Parse the ranges and add the resources found to the list */
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for_each_of_pci_range(&parser, &range) {
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if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
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dev_err(dev, "Maximum memory resources exceeded\n");
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return -EINVAL;
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}
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mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
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if (!mem) {
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err = -ENOMEM;
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goto free_resources;
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}
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of_pci_range_to_resource(&range, node, mem);
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switch (mem->flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_MEM:
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offset = range.cpu_addr - range.pci_addr;
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mem_resno++;
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break;
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default:
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err = -EINVAL;
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break;
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}
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if (err < 0) {
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dev_warn(dev, "Invalid resource found %pR\n", mem);
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continue;
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}
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err = request_resource(&iomem_resource, mem);
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if (err)
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goto free_resources;
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pci_add_resource_offset(&port->resources, mem, offset);
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}
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/* Get the bus range */
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if (of_pci_parse_bus_range(node, &port->bus_range)) {
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u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
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u8 last;
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last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
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XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
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port->bus_range = (struct resource) {
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.name = node->name,
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.start = 0,
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.end = last,
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.flags = IORESOURCE_BUS,
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};
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}
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/* Register bus resource */
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pci_add_resource(&port->resources, &port->bus_range);
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return 0;
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free_resources:
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release_child_resources(&iomem_resource);
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resource_list_for_each_entry(win, &port->resources)
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devm_kfree(dev, win->res);
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pci_free_resource_list(&port->resources);
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return err;
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}
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/**
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* xilinx_pcie_parse_dt - Parse Device tree
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* @port: PCIe port information
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@ -803,6 +708,8 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
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struct hw_pci hw;
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struct device *dev = &pdev->dev;
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int err;
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resource_size_t iobase = 0;
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LIST_HEAD(res);
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if (!dev->of_node)
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return -ENODEV;
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@ -827,14 +734,10 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
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return err;
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}
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/*
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* Parse PCI ranges, configuration bus range and
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* request their resources
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*/
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INIT_LIST_HEAD(&port->resources);
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err = xilinx_pcie_parse_and_add_res(port);
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err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, &res,
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&iobase);
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if (err) {
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dev_err(dev, "Failed adding resources\n");
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dev_err(dev, "Getting bridge resources failed\n");
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return err;
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}
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