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Merge branch 'omap/dt' into next/omap-gpmc

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Dependency for the gpmc changes

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-11-20 18:14:15 +01:00
commit 0233903e40
45 changed files with 1989 additions and 524 deletions
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3
arch/arm/boot/dts/Makefile
View File

@ -302,7 +302,9 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
omap3-ha.dtb \
omap3-ha-lcd.dtb \
omap3-igep0020.dtb \
omap3-igep0020-rev-f.dtb \
omap3-igep0030.dtb \
omap3-igep0030-rev-g.dtb \
omap3-ldp.dtb \
omap3-lilly-dbb056.dtb \
omap3-n900.dtb \
@ -347,6 +349,7 @@ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
omap5-sbc-t54.dtb \
omap5-uevm.dtb
dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
am57xx-beagle-x15.dtb \
dra72-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
orion5x-lacie-ethernet-disk-mini-v2.dtb \

4
arch/arm/boot/dts/am335x-evm.dts
View File

@ -437,9 +437,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;

4
arch/arm/boot/dts/am335x-igep0033.dtsi
View File

@ -126,10 +126,10 @@
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
gpmc,device-width = <1>;

7
arch/arm/boot/dts/am33xx.dtsi
View File

@ -204,6 +204,8 @@
reg = <0x44e09000 0x2000>;
interrupts = <72>;
status = "disabled";
dmas = <&edma 26>, <&edma 27>;
dma-names = "tx", "rx";
};
uart1: serial@48022000 {
@ -213,6 +215,8 @@
reg = <0x48022000 0x2000>;
interrupts = <73>;
status = "disabled";
dmas = <&edma 28>, <&edma 29>;
dma-names = "tx", "rx";
};
uart2: serial@48024000 {
@ -222,6 +226,8 @@
reg = <0x48024000 0x2000>;
interrupts = <74>;
status = "disabled";
dmas = <&edma 30>, <&edma 31>;
dma-names = "tx", "rx";
};
uart3: serial@481a6000 {
@ -356,6 +362,7 @@
reg = <0x480C8000 0x200>;
interrupts = <77>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: wkup_m3 {

1
arch/arm/boot/dts/am4372.dtsi
View File

@ -168,6 +168,7 @@
reg = <0x480C8000 0x200>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: wkup_m3 {

4
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -438,9 +438,9 @@
status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;

405
arch/arm/boot/dts/am57xx-beagle-x15.dts Normal file
View File

@ -0,0 +1,405 @@
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra74x.dtsi"
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "TI AM5728 BeagleBoard-X15";
compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
aliases {
rtc0 = &mcp_rtc;
rtc1 = &tps659038_rtc;
};
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
vdd_3v3: fixedregulator-vdd_3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <&regen1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vtt_fixed: fixedregulator-vtt {
/* TPS51200 */
compatible = "regulator-fixed";
regulator-name = "vtt_fixed";
vin-supply = <&smps3_reg>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>;
led@0 {
label = "beagle-x15:usr0";
gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led@1 {
label = "beagle-x15:usr1";
gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "cpu0";
default-state = "off";
};
led@2 {
label = "beagle-x15:usr2";
gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led@3 {
label = "beagle-x15:usr3";
gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "ide-disk";
default-state = "off";
};
};
};
&dra7_pmx_core {
leds_pins_default: leds_pins_default {
pinctrl-single,pins = <
0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
>;
};
i2c1_pins_default: i2c1_pins_default {
pinctrl-single,pins = <
0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
>;
};
i2c3_pins_default: i2c3_pins_default {
pinctrl-single,pins = <
0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
>;
};
uart3_pins_default: uart3_pins_default {
pinctrl-single,pins = <
0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
>;
};
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
tps659038_pins_default: tps659038_pins_default {
pinctrl-single,pins = <
0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
>;
};
tmp102_pins_default: tmp102_pins_default {
pinctrl-single,pins = <
0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
>;
};
mcp79410_pins_default: mcp79410_pins_default {
pinctrl-single,pins = <
0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_default>;
clock-frequency = <400000>;
tps659038: tps659038@58 {
compatible = "ti,tps659038";
reg = <0x58>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&tps659038_pins_default>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
regulators {
smps12_reg: smps12 {
/* VDD_MPU */
regulator-name = "smps12";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps3_reg: smps3 {
/* VDD_DDR */
regulator-name = "smps3";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
smps45_reg: smps45 {
/* VDD_DSPEVE, VDD_IVA, VDD_GPU */
regulator-name = "smps45";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
smps6_reg: smps6 {
/* VDD_CORE */
regulator-name = "smps6";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1030000>;
regulator-always-on;
regulator-boot-on;
};
/* SMPS7 unused */
smps8_reg: smps8 {
/* VDD_1V8 */
regulator-name = "smps8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* SMPS9 unused */
ldo1_reg: ldo1 {
/* VDD_SD */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
ldo2_reg: ldo2 {
/* VDD_SHV5 */
regulator-name = "ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo9_reg: ldo9 {
/* VDD_RTC */
regulator-name = "ldo9";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
};
ldoln_reg: ldoln {
/* VDDA_1V8_PLL */
regulator-name = "ldoln";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldousb_reg: ldousb {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldousb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
regen1: regen1 {
/* VDD_3V3_ON */
regulator-name = "regen1";
regulator-boot-on;
regulator-always-on;
};
};
};
tps659038_rtc: tps659038_rtc {
compatible = "ti,palmas-rtc";
interrupt-parent = <&tps659038>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
tps659038_pwr_button: tps659038_pwr_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps659038>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
ti,palmas-long-press-seconds = <12>;
};
};
tmp102: tmp102@48 {
compatible = "ti,tmp102";
reg = <0x48>;
pinctrl-names = "default";
pinctrl-0 = <&tmp102_pins_default>;
interrupt-parent = <&gpio7>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins_default>;
clock-frequency = <400000>;
mcp_rtc: rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */
pinctrl-names = "default";
pinctrl-0 = <&mcp79410_pins_default>;
vcc-supply = <&vdd_3v3>;
wakeup-source;
};
};
&gpio7 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&cpu0 {
cpu0-supply = <&smps12_reg>;
voltage-tolerance = <1>;
};
&uart3 {
status = "okay";
interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x248>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_default>;
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&ldo1_reg>;
vmmc_aux-supply = <&vdd_3v3>;
pbias-supply = <&pbias_mmc_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
&mmc2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&vdd_3v3>;
bus-width = <8>;
ti,non-removable;
cap-mmc-dual-data-rate;
};
&sata {
status = "okay";
};
&usb2_phy1 {
phy-supply = <&ldousb_reg>;
};
&usb1 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
};

111
arch/arm/boot/dts/dra7-evm.dts
View File

@ -171,6 +171,86 @@
0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
/* Slave 2 */
0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 */
0x250 (MUX_MODE15)
0x254 (MUX_MODE15)
0x258 (MUX_MODE15)
0x25c (MUX_MODE15)
0x260 (MUX_MODE15)
0x264 (MUX_MODE15)
0x268 (MUX_MODE15)
0x26c (MUX_MODE15)
0x270 (MUX_MODE15)
0x274 (MUX_MODE15)
0x278 (MUX_MODE15)
0x27c (MUX_MODE15)
/* Slave 2 */
0x198 (MUX_MODE15)
0x19c (MUX_MODE15)
0x1a0 (MUX_MODE15)
0x1a4 (MUX_MODE15)
0x1a8 (MUX_MODE15)
0x1ac (MUX_MODE15)
0x1b0 (MUX_MODE15)
0x1b4 (MUX_MODE15)
0x1b8 (MUX_MODE15)
0x1bc (MUX_MODE15)
0x1c0 (MUX_MODE15)
0x1c4 (MUX_MODE15)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
0x23c (MUX_MODE15)
0x240 (MUX_MODE15)
>;
};
};
&i2c1 {
@ -201,6 +281,7 @@
regulator-name = "smps45";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
@ -209,6 +290,7 @@
regulator-name = "smps6";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <12500000>;
regulator-always-on;
regulator-boot-on;
};
@ -226,6 +308,7 @@
regulator-name = "smps8";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
@ -252,6 +335,7 @@
regulator-name = "ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
@ -269,6 +353,7 @@
regulator-name = "ldo9";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
};
@ -528,3 +613,29 @@
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <2>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
};

167
arch/arm/boot/dts/dra7.dtsi
View File

@ -34,6 +34,12 @@
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
serial6 = &uart7;
serial7 = &uart8;
serial8 = &uart9;
serial9 = &uart10;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
};
timer {
@ -335,6 +341,8 @@
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&sdma 49>, <&sdma 50>;
dma-names = "tx", "rx";
};
uart2: serial@4806c000 {
@ -344,6 +352,8 @@
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&sdma 51>, <&sdma 52>;
dma-names = "tx", "rx";
};
uart3: serial@48020000 {
@ -353,6 +363,8 @@
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&sdma 53>, <&sdma 54>;
dma-names = "tx", "rx";
};
uart4: serial@4806e000 {
@ -362,6 +374,8 @@
ti,hwmods = "uart4";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&sdma 55>, <&sdma 56>;
dma-names = "tx", "rx";
};
uart5: serial@48066000 {
@ -371,6 +385,8 @@
ti,hwmods = "uart5";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&sdma 63>, <&sdma 64>;
dma-names = "tx", "rx";
};
uart6: serial@48068000 {
@ -380,6 +396,8 @@
ti,hwmods = "uart6";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&sdma 79>, <&sdma 80>;
dma-names = "tx", "rx";
};
uart7: serial@48420000 {
@ -421,7 +439,11 @@
mailbox1: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox1";
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
status = "disabled";
@ -430,7 +452,12 @@
mailbox2: mailbox@4883a000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883a000 0x200>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox2";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -439,7 +466,12 @@
mailbox3: mailbox@4883c000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883c000 0x200>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox3";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -448,7 +480,12 @@
mailbox4: mailbox@4883e000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883e000 0x200>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox4";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -457,7 +494,12 @@
mailbox5: mailbox@48840000 {
compatible = "ti,omap4-mailbox";
reg = <0x48840000 0x200>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox5";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -466,7 +508,12 @@
mailbox6: mailbox@48842000 {
compatible = "ti,omap4-mailbox";
reg = <0x48842000 0x200>;
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox6";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -475,7 +522,12 @@
mailbox7: mailbox@48844000 {
compatible = "ti,omap4-mailbox";
reg = <0x48844000 0x200>;
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox7";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -484,7 +536,12 @@
mailbox8: mailbox@48846000 {
compatible = "ti,omap4-mailbox";
reg = <0x48846000 0x200>;
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox8";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -493,7 +550,12 @@
mailbox9: mailbox@4885e000 {
compatible = "ti,omap4-mailbox";
reg = <0x4885e000 0x200>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox9";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -502,7 +564,12 @@
mailbox10: mailbox@48860000 {
compatible = "ti,omap4-mailbox";
reg = <0x48860000 0x200>;
interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox10";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -511,7 +578,12 @@
mailbox11: mailbox@48862000 {
compatible = "ti,omap4-mailbox";
reg = <0x48862000 0x200>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox11";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -520,7 +592,12 @@
mailbox12: mailbox@48864000 {
compatible = "ti,omap4-mailbox";
reg = <0x48864000 0x200>;
interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox12";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -529,7 +606,12 @@
mailbox13: mailbox@48802000 {
compatible = "ti,omap4-mailbox";
reg = <0x48802000 0x200>;
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox13";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
@ -1141,7 +1223,7 @@
};
};
omap_dwc3_1@48880000 {
omap_dwc3_1: omap_dwc3_1@48880000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss1";
reg = <0x48880000 0x10000>;
@ -1162,7 +1244,7 @@
};
};
omap_dwc3_2@488c0000 {
omap_dwc3_2: omap_dwc3_2@488c0000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss2";
reg = <0x488c0000 0x10000>;
@ -1184,7 +1266,7 @@
};
/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
omap_dwc3_3@48900000 {
omap_dwc3_3: omap_dwc3_3@48900000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss3";
reg = <0x48900000 0x10000>;
@ -1204,26 +1286,6 @@
};
};
omap_dwc3_4@48940000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss4";
reg = <0x48940000 0x10000>;
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
status = "disabled";
usb4: usb@48950000 {
compatible = "snps,dwc3";
reg = <0x48950000 0x17000>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
elm: elm@48078000 {
compatible = "ti,am3352-elm";
reg = <0x48078000 0xfc0>; /* device IO registers */
@ -1265,6 +1327,65 @@
ti,irqs-skip = <10 133 139 140>;
ti,irqs-safe-map = <0>;
};
mac: ethernet@4a100000 {
compatible = "ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
#size-cells = <1>;
/*
* rx_thresh_pend
* rx_pend
* tx_pend
* misc_pend
*/
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
ranges;
status = "disabled";
davinci_mdio: mdio@48485000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x48485000 0x100>;
};
cpsw_emac0: slave@48480200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@48480300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@4a002554 {
compatible = "ti,dra7xx-cpsw-phy-sel";
reg= <0x4a002554 0x4>;
reg-names = "gmii-sel";
};
};
};
};

296
arch/arm/boot/dts/dra72-evm.dts
View File

@ -17,6 +17,13 @@
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1024 MB */
};
evm_3v3: fixedregulator-evm_3v3 {
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&dra7_pmx_core {
@ -26,6 +33,78 @@
0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
>;
};
nand_default: nand_default {
pinctrl-single,pins = <
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
usb2_pins: pinmux_usb2_pins {
pinctrl-single,pins = <
0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
>;
};
tps65917_pins_default: tps65917_pins_default {
pinctrl-single,pins = <
0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
>;
};
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
};
&i2c1 {
@ -38,6 +117,9 @@
compatible = "ti,tps65917";
reg = <0x58>;
pinctrl-names = "default";
pinctrl-0 = <&tps65917_pins_default>;
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
interrupt-parent = <&gic>;
interrupt-controller;
@ -136,9 +218,223 @@
};
};
};
tps65917_power_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps65917>;
interrupts = <1 IRQ_TYPE_NONE>;
wakeup-source;
ti,palmas-long-press-seconds = <6>;
};
};
};
&uart1 {
status = "okay";
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_default>;
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.1 (NAND_SELn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
reg = <0 0 4>; /* device IO registers */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <40>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000c0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001c0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001e0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x0f600000>;
};
};
};
&usb2_phy1 {
phy-supply = <&ldo4_reg>;
};
&usb2_phy2 {
phy-supply = <&ldo4_reg>;
};
&usb1 {
dr_mode = "peripheral";
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
};
&usb2 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb2_pins>;
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is a viable alternative
*/
cd-gpios = <&gpio6 27 0>;
};
&mmc2 {
/* SW5-3 in ON position */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&evm_3v3>;
bus-width = <8>;
ti,non-removable;
};
&dra7_pmx_core {
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 2 */
0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 2 */
0x198 (MUX_MODE15)
0x19c (MUX_MODE15)
0x1a0 (MUX_MODE15)
0x1a4 (MUX_MODE15)
0x1a8 (MUX_MODE15)
0x1ac (MUX_MODE15)
0x1b0 (MUX_MODE15)
0x1b4 (MUX_MODE15)
0x1b8 (MUX_MODE15)
0x1bc (MUX_MODE15)
0x1c0 (MUX_MODE15)
0x1c4 (MUX_MODE15)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
0x23c (MUX_MODE15)
0x240 (MUX_MODE15)
>;
};
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
active_slave = <1>;
};

22
arch/arm/boot/dts/dra74x.dtsi
View File

@ -44,4 +44,26 @@
interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
};
ocp {
omap_dwc3_4: omap_dwc3_4@48940000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss4";
reg = <0x48940000 0x10000>;
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
status = "disabled";
usb4: usb@48950000 {
compatible = "snps,dwc3";
reg = <0x48950000 0x17000>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
};
};

41
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
View File

@ -23,24 +23,29 @@
ethernet@gpmc {
compatible = "smsc,lan9221", "smsc,lan9115";
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <1>;
gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <180>;
gpmc,adv-rd-off-ns = <18>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <90>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
gpmc,device-width = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <150>;
gpmc,cs-wr-off-ns = <150>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <15>;
gpmc,adv-wr-off-ns = <40>;
gpmc,oe-on-ns = <45>;
gpmc,oe-off-ns = <140>;
gpmc,we-on-ns = <45>;
gpmc,we-off-ns = <140>;
gpmc,rd-cycle-ns = <155>;
gpmc,wr-cycle-ns = <155>;
gpmc,access-ns = <120>;
gpmc,page-burst-access-ns = <20>;
gpmc,bus-turnaround-ns = <75>;
gpmc,cycle2cycle-delay-ns = <75>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
gpmc,wr-access-ns = <0>;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;

62
arch/arm/boot/dts/omap-zoom-common.dtsi
View File

@ -5,7 +5,7 @@
#include "omap-gpmc-smsc911x.dtsi"
&gpmc {
ranges = <3 0 0x10000000 0x00000400>,
ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */
<7 0 0x2c000000 0x01000000>;
/*
@ -15,7 +15,65 @@
*/
uart@3,0 {
compatible = "ns16550a";
reg = <3 0 0x100>;
reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio4>;
interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <155>;
gpmc,cs-wr-off-ns = <155>;
gpmc,adv-on-ns = <15>;
gpmc,adv-rd-off-ns = <40>;
gpmc,adv-wr-off-ns = <40>;
gpmc,oe-on-ns = <45>;
gpmc,oe-off-ns = <145>;
gpmc,we-on-ns = <45>;
gpmc,we-off-ns = <145>;
gpmc,rd-cycle-ns = <155>;
gpmc,wr-cycle-ns = <155>;
gpmc,access-ns = <145>;
gpmc,page-burst-access-ns = <20>;
gpmc,bus-turnaround-ns = <20>;
gpmc,cycle2cycle-delay-ns = <20>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <45>;
gpmc,wr-access-ns = <145>;
};
uart@3,1 {
compatible = "ns16550a";
reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio4>;
interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
};
uart@3,2 {
compatible = "ns16550a";
reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;
interrupt-parent = <&gpio4>;
interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
clock-frequency = <1843200>;
current-speed = <115200>;
};
uart@3,3 {
compatible = "ns16550a";
reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */
bank-width = <2>;
reg-shift = <1>;
reg-io-width = <1>;

4
arch/arm/boot/dts/omap2420-n8x0-common.dtsi
View File

@ -40,14 +40,14 @@
};
&gpmc {
ranges = <0 0 0x04000000 0x10000000>;
ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
/* gpio-irq for dma: 26 */
onenand@0,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x10000000>;
reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
gpmc,sync-read;
gpmc,burst-length = <16>;

1
arch/arm/boot/dts/omap2420.dtsi
View File

@ -157,6 +157,7 @@
interrupts = <26>, <34>;
interrupt-names = "dsp", "iva";
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
mbox_dsp: dsp {

28
arch/arm/boot/dts/omap2430-sdp.dts
View File

@ -43,7 +43,31 @@
interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */
reg = <5 0x300 0xf>;
bank-width = <2>;
gpmc,mux-add-data;
};
gpmc,sync-clk-ps = <0>;
gpmc,mux-add-data = <2>;
gpmc,device-width = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cs-on-ns = <7>;
gpmc,cs-rd-off-ns = <233>;
gpmc,cs-wr-off-ns = <233>;
gpmc,adv-on-ns = <22>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,oe-on-ns = <67>;
gpmc,oe-off-ns = <210>;
gpmc,we-on-ns = <67>;
gpmc,we-off-ns = <210>;
gpmc,rd-cycle-ns = <233>;
gpmc,wr-cycle-ns = <233>;
gpmc,access-ns = <233>;
gpmc,page-burst-access-ns = <30>;
gpmc,bus-turnaround-ns = <30>;
gpmc,cycle2cycle-delay-ns = <30>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
gpmc,wr-access-ns = <0>;
};
};

1
arch/arm/boot/dts/omap2430.dtsi
View File

@ -247,6 +247,7 @@
reg = <0x48094000 0x200>;
interrupts = <26>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
mbox_dsp: dsp {

11
arch/arm/boot/dts/omap3-cm-t3517.dts
View File

@ -134,3 +134,14 @@
bus-width = <4>;
cap-power-off-card;
};
&dss {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <
&dss_dpi_pins_common
&dss_dpi_pins_cm_t35x
>;
};

11
arch/arm/boot/dts/omap3-cm-t3530.dts
View File

@ -46,3 +46,14 @@
bus-width = <4>;
cap-power-off-card;
};
&dss {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <
&dss_dpi_pins_common
&dss_dpi_pins_cm_t35x
>;
};

24
arch/arm/boot/dts/omap3-cm-t3730.dts
View File

@ -31,6 +31,19 @@
};
};
&omap3_pmx_wkup {
dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
>;
};
};
&omap3_pmx_core {
mmc2_pins: pinmux_mmc2_pins {
@ -61,3 +74,14 @@
bus-width = <4>;
cap-power-off-card;
};
&dss {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <
&dss_dpi_pins_common
&dss_dpi_pins_cm_t3730
>;
};

39
arch/arm/boot/dts/omap3-cm-t3x.dtsi
View File

@ -76,6 +76,45 @@
OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */
>;
};
dss_dpi_pins_common: pinmux_dss_dpi_pins_common {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
>;
};
};
&uart3 {

4
arch/arm/boot/dts/omap3-devkit8000.dts
View File

@ -106,10 +106,10 @@
};
&gpmc {
ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
gpmc,sync-clk-ps = <0>;

5
arch/arm/boot/dts/omap3-evm-37xx.dts
View File

@ -154,13 +154,14 @@
};
&gpmc {
ranges = <0 0 0x00000000 0x20000000>,
ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */
<5 0 0x2c000000 0x01000000>;
nand@0,0 {
linux,mtd-name= "hynix,h8kds0un0mer-4em";
reg = <0 0 0>;
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;

86
arch/arm/boot/dts/omap3-gta04.dtsi
View File

@ -104,67 +104,67 @@
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */
OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
>;
};
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
};
@ -397,10 +397,10 @@
};
&gpmc {
ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";

103
arch/arm/boot/dts/omap3-igep.dtsi
View File

@ -31,18 +31,6 @@
regulator-always-on;
};
lbee1usjyc_vmmc: lbee1usjyc_vmmc {
pinctrl-names = "default";
pinctrl-0 = <&lbee1usjyc_pins>;
compatible = "regulator-fixed";
regulator-name = "regulator-lbee1usjyc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */
startup-delay-us = <10000>;
enable-active-high;
vin-supply = <&vdd33>;
};
};
&omap3_pmx_core {
@ -53,13 +41,6 @@
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
@ -67,15 +48,6 @@
>;
};
/* WiFi/BT combo */
lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
pinctrl-single,pins = <
0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */
0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
@ -120,13 +92,6 @@
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
@ -135,6 +100,55 @@
};
};
&gpmc {
nand@0,0 {
linux,mtd-name= "micron,mt29c4g96maz";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SPL";
reg = <0 0x100000>;
};
partition@80000 {
label = "U-Boot";
reg = <0x100000 0x180000>;
};
partition@1c0000 {
label = "Environment";
reg = <0x280000 0x100000>;
};
partition@280000 {
label = "Kernel";
reg = <0x380000 0x300000>;
};
partition@780000 {
label = "Filesystem";
reg = <0x680000 0x1f980000>;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@ -156,12 +170,6 @@
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
@ -181,14 +189,6 @@
bus-width = <4>;
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&lbee1usjyc_vmmc>;
bus-width = <4>;
non-removable;
};
&mmc3 {
status = "disabled";
};
@ -198,11 +198,6 @@
pinctrl-0 = <&uart1_pins>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;

246
arch/arm/boot/dts/omap3-igep0020-common.dtsi Normal file
View File

@ -0,0 +1,246 @@
/*
* Common Device Tree Source for IGEPv2
*
* Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "omap3-igep.dtsi"
#include "omap-gpmc-smsc9221.dtsi"
/ {
leds {
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
compatible = "gpio-leds";
boot {
label = "omap3:green:boot";
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
user0 {
label = "omap3:red:user0";
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
user1 {
label = "omap3:red:user1";
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
user2 {
label = "omap3:green:user1";
gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
};
};
/* HS USB Port 1 Power */
hsusb1_power: hsusb1_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb1_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
startup-delay-us = <70000>;
};
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
vcc-supply = <&hsusb1_power>;
};
tfp410: encoder@0 {
compatible = "ti,tfp410";
powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint@0 {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint@0 {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector@0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
};
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&tfp410_pins
&dss_dpi_pins
>;
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
>;
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <
&hsusbb1_pins
>;
hsusbb1_pins: pinmux_hsusbb1_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
>;
};
};
&i2c3 {
clock-frequency = <100000>;
/*
* Display monitor features are burnt in the EEPROM
* as EDID data.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&gpmc {
ranges = <0 0 0x00000000 0x20000000>,
<5 0 0x2c000000 0x01000000>;
ethernet@gpmc {
pinctrl-names = "default";
pinctrl-0 = <&smsc9221_pins>;
reg = <5 0 0xff>;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
&usbhshost {
port1-mode = "ehci-phy";
};
&usbhsehci {
phys = <&hsusb1_phy>;
};
&vpll2 {
/* Needed for DSS */
regulator-name = "vdds_dsi";
};
&dss {
status = "ok";
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};

45
arch/arm/boot/dts/omap3-igep0020-rev-f.dts Normal file
View File

@ -0,0 +1,45 @@
/*
* Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x)
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "omap3-igep0020-common.dtsi"
/ {
model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
compatible = "regulator-fixed";
regulator-name = "regulator-lbep5clwmc-wlen";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */
enable-active-high;
};
};
&omap3_pmx_core {
lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */
OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */
OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */
>;
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
vmmc-supply = <&lbep5clwmc_wlen>;
bus-width = <4>;
non-removable;
};

303
arch/arm/boot/dts/omap3-igep0020.dts
View File

@ -1,5 +1,5 @@
/*
* Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x)
* Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@ -9,272 +9,59 @@
* published by the Free Software Foundation.
*/
#include "omap3-igep.dtsi"
#include "omap-gpmc-smsc9221.dtsi"
#include "omap3-igep0020-common.dtsi"
/ {
model = "IGEPv2 (TI OMAP AM/DM37x)";
model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
leds {
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
compatible = "gpio-leds";
boot {
label = "omap3:green:boot";
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
user0 {
label = "omap3:red:user0";
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
user1 {
label = "omap3:red:user1";
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
user2 {
label = "omap3:green:user1";
gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
};
/* Regulator to trigger the WIFI_PDN signal of the Wifi module */
lbee1usjyc_pdn: lbee1usjyc_pdn {
compatible = "regulator-fixed";
regulator-name = "regulator-lbee1usjyc-pdn";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */
startup-delay-us = <10000>;
enable-active-high;
};
/* HS USB Port 1 Power */
hsusb1_power: hsusb1_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb1_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
startup-delay-us = <70000>;
};
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
vcc-supply = <&hsusb1_power>;
};
tfp410: encoder@0 {
compatible = "ti,tfp410";
powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint@0 {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint@0 {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector@0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
/* Regulator to trigger the RESET_N_W signal of the Wifi module */
lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
compatible = "regulator-fixed";
regulator-name = "regulator-lbee1usjyc-reset-n-w";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */
enable-active-high;
};
};
&omap3_pmx_core {
lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
>;
};
};
/* On board Wifi module */
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <
&tfp410_pins
&dss_dpi_pins
>;
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <
&hsusbb1_pins
>;
hsusbb1_pins: pinmux_hsusbb1_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
>;
};
};
&i2c3 {
clock-frequency = <100000>;
/*
* Display monitor features are burnt in the EEPROM
* as EDID data.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&gpmc {
ranges = <0 0 0x00000000 0x20000000>,
<5 0 0x2c000000 0x01000000>;
nand@0,0 {
linux,mtd-name= "micron,mt29c4g96maz";
reg = <0 0 0>;
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SPL";
reg = <0 0x100000>;
};
partition@80000 {
label = "U-Boot";
reg = <0x100000 0x180000>;
};
partition@1c0000 {
label = "Environment";
reg = <0x280000 0x100000>;
};
partition@280000 {
label = "Kernel";
reg = <0x380000 0x300000>;
};
partition@780000 {
label = "Filesystem";
reg = <0x680000 0x1f980000>;
};
};
ethernet@gpmc {
pinctrl-names = "default";
pinctrl-0 = <&smsc9221_pins>;
reg = <5 0 0xff>;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
};
&usbhshost {
port1-mode = "ehci-phy";
};
&usbhsehci {
phys = <&hsusb1_phy>;
};
&vpll2 {
/* Needed for DSS */
regulator-name = "vdds_dsi";
};
&dss {
status = "ok";
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
vmmc-supply = <&lbee1usjyc_pdn>;
vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
bus-width = <4>;
non-removable;
};

60
arch/arm/boot/dts/omap3-igep0030-common.dtsi Normal file
View File

@ -0,0 +1,60 @@
/*
* Common Device Tree Source for IGEP COM MODULE
*
* Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "omap3-igep.dtsi"
/ {
leds: gpio_leds {
compatible = "gpio-leds";
user0 {
label = "omap3:red:user0";
gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
default-state = "off";
};
user1 {
label = "omap3:green:user1";
gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
default-state = "off";
};
user2 {
label = "omap3:red:user1";
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */
default-state = "off";
};
};
};
&omap3_pmx_core {
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
>;
};
};
&omap3_pmx_core2 {
leds_core2_pins: pinmux_leds_core2_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};

67
arch/arm/boot/dts/omap3-igep0030-rev-g.dts Normal file
View File

@ -0,0 +1,67 @@
/*
* Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)
*
* Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "omap3-igep0030-common.dtsi"
/ {
model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
compatible = "regulator-fixed";
regulator-name = "regulator-lbep5clwmc-wlen";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */
enable-active-high;
};
};
&omap3_pmx_core {
lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */
OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */
OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */
>;
};
};
&i2c2 {
status = "disabled";
};
&leds {
pinctrl-names = "default";
pinctrl-0 = <&leds_pins &leds_core2_pins>;
boot {
label = "omap3:green:boot";
gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
vmmc-supply = <&lbep5clwmc_wlen>;
bus-width = <4>;
non-removable;
};

123
arch/arm/boot/dts/omap3-igep0030.dts
View File

@ -1,5 +1,5 @@
/*
* Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x)
* Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@ -9,97 +9,62 @@
* published by the Free Software Foundation.
*/
#include "omap3-igep.dtsi"
#include "omap3-igep0030-common.dtsi"
/ {
model = "IGEP COM MODULE (TI OMAP AM/DM37x)";
model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
leds {
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
compatible = "gpio-leds";
/* Regulator to trigger the WIFI_PDN signal of the Wifi module */
lbee1usjyc_pdn: lbee1usjyc_pdn {
compatible = "regulator-fixed";
regulator-name = "regulator-lbee1usjyc-pdn";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */
startup-delay-us = <10000>;
enable-active-high;
};
boot {
label = "omap3:green:boot";
gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
default-state = "on";
};
user0 {
label = "omap3:red:user0";
gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
default-state = "off";
};
user1 {
label = "omap3:green:user1";
gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
default-state = "off";
};
user2 {
label = "omap3:red:user1";
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
default-state = "off";
};
/* Regulator to trigger the RESET_N_W signal of the Wifi module */
lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
compatible = "regulator-fixed";
regulator-name = "regulator-lbee1usjyc-reset-n-w";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */
enable-active-high;
};
};
&omap3_pmx_core2 {
leds_pins: pinmux_leds_pins {
&omap3_pmx_core {
lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
>;
};
};
&gpmc {
ranges = <0 0 0x00000000 0x20000000>;
&leds {
pinctrl-names = "default";
pinctrl-0 = <&leds_core2_pins>;
nand@0,0 {
linux,mtd-name= "micron,mt29c4g96maz";
reg = <0 0 0>;
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SPL";
reg = <0 0x100000>;
};
partition@80000 {
label = "U-Boot";
reg = <0x100000 0x180000>;
};
partition@1c0000 {
label = "Environment";
reg = <0x280000 0x100000>;
};
partition@280000 {
label = "Kernel";
reg = <0x380000 0x300000>;
};
partition@780000 {
label = "Filesystem";
reg = <0x680000 0x1f980000>;
};
boot {
label = "omap3:green:boot";
gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */
default-state = "on";
};
};
/* On board Wifi module */
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
vmmc-supply = <&lbee1usjyc_pdn>;
vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
bus-width = <4>;
non-removable;
};

3
arch/arm/boot/dts/omap3-ldp.dts
View File

@ -101,8 +101,9 @@
nand@0,0 {
linux,mtd-name= "micron,nand";
reg = <0 0 0>;
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;

2
arch/arm/boot/dts/omap3-lilly-a83x.dtsi
View File

@ -363,7 +363,7 @@
<7 0 0x15000000 0x01000000>;
nand@0,0 {
reg = <0 0 0x1000000>;
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
/* no elm on omap3 */

35
arch/arm/boot/dts/omap3-n900.dts
View File

@ -142,6 +142,33 @@
>;
};
gpmc_pins: pinmux_gpmc_pins {
pinctrl-single,pins = <
/* address lines */
OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
/* data lines, gpmc_d0..d7 not muxable according to TRM */
OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
/*
* gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
* according to TRM. OneNAND seems to require PIN_INPUT on clock.
*/
OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
@ -585,16 +612,16 @@
};
&gpmc {
ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
<1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
pinctrl-names = "default";
pinctrl-0 = <&gpmc_pins>;
/* gpio-irq for dma: 65 */
/* sys_ndmareq1 could be used by the driver, not as gpio65 though */
onenand@0,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x10000000>;
reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
gpmc,sync-read;
gpmc,sync-write;

4
arch/arm/boot/dts/omap3-n950-n9.dtsi
View File

@ -115,12 +115,12 @@
};
&gpmc {
ranges = <0 0 0x04000000 0x20000000>;
ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
onenand@0,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x20000000>;
reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
gpmc,sync-read;
gpmc,sync-write;

90
arch/arm/boot/dts/omap3-sb-t35.dtsi
View File

@ -2,6 +2,49 @@
* Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
*/
/ {
tfp410: encoder@0 {
compatible = "ti,tfp410";
powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */
pinctrl-names = "default";
pinctrl-0 = <&tfp410_pins>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint@0 {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint@0 {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector@0 {
compatible = "dvi-connector";
label = "dvi";
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
};
&omap3_pmx_core {
smsc2_pins: pinmux_smsc2_pins {
pinctrl-single,pins = <
@ -9,6 +52,12 @@
OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */
>;
};
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
>;
};
};
&gpmc {
@ -22,24 +71,29 @@
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
reg = <4 0 0xff>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <1>;
gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <180>;
gpmc,adv-rd-off-ns = <18>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <90>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
gpmc,device-width = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <150>;
gpmc,cs-wr-off-ns = <150>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <15>;
gpmc,adv-wr-off-ns = <40>;
gpmc,oe-on-ns = <45>;
gpmc,oe-off-ns = <140>;
gpmc,we-on-ns = <45>;
gpmc,we-off-ns = <140>;
gpmc,rd-cycle-ns = <155>;
gpmc,wr-cycle-ns = <155>;
gpmc,access-ns = <120>;
gpmc,page-burst-access-ns = <20>;
gpmc,bus-turnaround-ns = <75>;
gpmc,cycle2cycle-delay-ns = <75>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
gpmc,wr-access-ns = <0>;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;

14
arch/arm/boot/dts/omap3-sbc-t3517.dts
View File

@ -9,6 +9,10 @@
model = "CompuLab SBC-T3517 with CM-T3517";
compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
aliases {
display0 = &dvi0;
};
/* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
vddvario: regulator-vddvario-sb-t35 {
compatible = "regulator-fixed";
@ -54,3 +58,13 @@
wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */
cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */
};
&dss {
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};

14
arch/arm/boot/dts/omap3-sbc-t3530.dts
View File

@ -8,6 +8,10 @@
/ {
model = "CompuLab SBC-T3530 with CM-T3530";
compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
aliases {
display0 = &dvi0;
};
};
&omap3_pmx_core {
@ -34,3 +38,13 @@
&mmc1 {
cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
};
&dss {
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};

14
arch/arm/boot/dts/omap3-sbc-t3730.dts
View File

@ -8,6 +8,10 @@
/ {
model = "CompuLab SBC-T3730 with CM-T3730";
compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
aliases {
display0 = &dvi0;
};
};
&omap3_pmx_core {
@ -25,3 +29,13 @@
ranges = <5 0 0x2c000000 0x01000000>,
<4 0 0x2d000000 0x01000000>;
};
&dss {
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};

2
arch/arm/boot/dts/omap3-tao3530.dtsi
View File

@ -270,7 +270,7 @@
ranges = <0 0 0x00000000 0x01000000>;
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <16>;
gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
ti,nand-ecc-opt = "sw";

1
arch/arm/boot/dts/omap3.dtsi
View File

@ -332,6 +332,7 @@
ti,hwmods = "mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
#mbox-cells = <1>;
ti,mbox-num-users = <2>;
ti,mbox-num-fifos = <2>;
mbox_dsp: dsp {

8
arch/arm/boot/dts/omap3430-sdp.dts
View File

@ -51,8 +51,8 @@
&gpmc {
ranges = <0 0 0x10000000 0x08000000>,
<1 0 0x28000000 0x08000000>,
<2 0 0x20000000 0x10000000>;
<1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
<2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */
nor@0,0 {
compatible = "cfi-flash";
@ -106,7 +106,7 @@
linux,mtd-name= "micron,mt29f1g08abb";
#address-cells = <1>;
#size-cells = <1>;
reg = <1 0 0x08000000>;
reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
ti,nand-ecc-opt = "sw";
nand-bus-width = <8>;
gpmc,cs-on-ns = <0>;
@ -150,7 +150,7 @@
linux,mtd-name= "samsung,kfm2g16q2m-deb8";
#address-cells = <1>;
#size-cells = <1>;
reg = <2 0 0x10000000>;
reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */
gpmc,device-width = <2>;
gpmc,mux-add-data = <2>;

1
arch/arm/boot/dts/omap4.dtsi
View File

@ -661,6 +661,7 @@
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
mbox_ipu: mbox_ipu {

1
arch/arm/boot/dts/omap5.dtsi
View File

@ -651,6 +651,7 @@
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
mbox_ipu: mbox_ipu {

36
arch/arm/mach-omap2/pdata-quirks.c
View File

@ -13,6 +13,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/ti_wilink_st.h>
#include <linux/wl12xx.h>
#include <linux/platform_data/pinctrl-single.h>
@ -139,8 +140,38 @@ static void __init omap3_sbc_t3530_legacy_init(void)
omap_ads7846_init(1, 57, 0, NULL);
}
static void __init omap3_igep0020_legacy_init(void)
struct ti_st_plat_data wilink_pdata = {
.nshutdown_gpio = 137,
.dev_name = "/dev/ttyO1",
.flow_cntrl = 1,
.baud_rate = 300000,
};
static struct platform_device wl18xx_device = {
.name = "kim",
.id = -1,
.dev = {
.platform_data = &wilink_pdata,
}
};
static struct platform_device btwilink_device = {
.name = "btwilink",
.id = -1,
};
static void __init omap3_igep0020_rev_f_legacy_init(void)
{
legacy_init_wl12xx(0, 0, 177);
platform_device_register(&wl18xx_device);
platform_device_register(&btwilink_device);
}
static void __init omap3_igep0030_rev_g_legacy_init(void)
{
legacy_init_wl12xx(0, 0, 136);
platform_device_register(&wl18xx_device);
platform_device_register(&btwilink_device);
}
static void __init omap3_evm_legacy_init(void)
@ -390,7 +421,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
{ "nokia,omap3-n900", nokia_n900_legacy_init, },
{ "nokia,omap3-n9", hsmmc2_internal_input_clk, },
{ "nokia,omap3-n950", hsmmc2_internal_input_clk, },
{ "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
{ "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
{ "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
{ "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
{ "ti,omap3-zoom3", omap3_zoom_legacy_init, },
{ "ti,am3517-evm", am3517_evm_legacy_init, },