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drm/i915: Split the BDW/HSW specific shared pll selection
We'll need a different algorithm to select the shared DPLL. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -708,23 +708,10 @@ intel_ddi_calculate_wrpll(int clock /* in Hz */,
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*r2_out = best.r2;
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}
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/*
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* Tries to find a *shared* PLL for the CRTC and store it in
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* intel_crtc->ddi_pll_sel.
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*
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* For private DPLLs, compute_config() should do the selection for us. This
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* function should be folded into compute_config() eventually.
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*/
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bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
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static bool
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hsw_ddi_pll_select(struct intel_crtc *intel_crtc, int output, int clock)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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int type = intel_encoder->type;
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int clock = intel_crtc->config.port_clock;
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intel_put_shared_dpll(intel_crtc);
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if (type == INTEL_OUTPUT_HDMI) {
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if (output == INTEL_OUTPUT_HDMI) {
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struct intel_shared_dpll *pll;
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uint32_t val;
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unsigned p, n2, r2;
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@ -750,6 +737,26 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
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return true;
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}
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/*
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* Tries to find a *shared* PLL for the CRTC and store it in
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* intel_crtc->ddi_pll_sel.
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*
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* For private DPLLs, compute_config() should do the selection for us. This
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* function should be folded into compute_config() eventually.
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*/
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bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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int type = intel_encoder->type;
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int clock = intel_crtc->config.port_clock;
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intel_put_shared_dpll(intel_crtc);
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return hsw_ddi_pll_select(intel_crtc, type, clock);
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}
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void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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