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drm/tegra: sor: Remove unnecessary conditional
Checking for sor->aux in eDP specific code is unnecessary because eDP inherently requires a valid AUX channel. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -1196,6 +1196,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
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struct tegra_sor *sor = to_sor(output);
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struct tegra_sor_config config;
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struct drm_dp_link link;
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u8 rate, lanes;
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int err = 0;
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u32 value;
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@ -1208,17 +1209,14 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
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if (output->panel)
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drm_panel_prepare(output->panel);
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if (sor->aux) {
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err = drm_dp_aux_enable(sor->aux);
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if (err < 0)
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dev_err(sor->dev, "failed to enable DP: %d\n", err);
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err = drm_dp_aux_enable(sor->aux);
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if (err < 0)
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dev_err(sor->dev, "failed to enable DP: %d\n", err);
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err = drm_dp_link_probe(sor->aux, &link);
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if (err < 0) {
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dev_err(sor->dev, "failed to probe eDP link: %d\n",
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err);
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return;
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}
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err = drm_dp_link_probe(sor->aux, &link);
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if (err < 0) {
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dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
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return;
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}
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err = clk_set_parent(sor->clk, sor->clk_safe);
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@ -1430,61 +1428,52 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
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value |= SOR_DP_PADCTL_PAD_CAL_PD;
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tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
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if (sor->aux) {
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u8 rate, lanes;
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err = drm_dp_link_probe(sor->aux, &link);
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if (err < 0)
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dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
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err = drm_dp_link_probe(sor->aux, &link);
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if (err < 0)
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dev_err(sor->dev, "failed to probe eDP link: %d\n",
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err);
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err = drm_dp_link_power_up(sor->aux, &link);
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if (err < 0)
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dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
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err = drm_dp_link_power_up(sor->aux, &link);
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if (err < 0)
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dev_err(sor->dev, "failed to power up eDP link: %d\n",
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err);
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err = drm_dp_link_configure(sor->aux, &link);
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if (err < 0)
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dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
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err = drm_dp_link_configure(sor->aux, &link);
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if (err < 0)
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dev_err(sor->dev, "failed to configure eDP link: %d\n",
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err);
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rate = drm_dp_link_rate_to_bw_code(link.rate);
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lanes = link.num_lanes;
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rate = drm_dp_link_rate_to_bw_code(link.rate);
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lanes = link.num_lanes;
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value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
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value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
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value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
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tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
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value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
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value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
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value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
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tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
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value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
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value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
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value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
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value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
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value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
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value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
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if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
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value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
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if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
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value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
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tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
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tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
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/* disable training pattern generator */
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/* disable training pattern generator */
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for (i = 0; i < link.num_lanes; i++) {
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unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
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SOR_DP_TPG_SCRAMBLER_GALIOS |
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SOR_DP_TPG_PATTERN_NONE;
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value = (value << 8) | lane;
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}
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tegra_sor_writel(sor, value, SOR_DP_TPG);
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err = tegra_sor_dp_train_fast(sor, &link);
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if (err < 0) {
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dev_err(sor->dev, "DP fast link training failed: %d\n",
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err);
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}
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dev_dbg(sor->dev, "fast link training succeeded\n");
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for (i = 0; i < link.num_lanes; i++) {
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unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
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SOR_DP_TPG_SCRAMBLER_GALIOS |
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SOR_DP_TPG_PATTERN_NONE;
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value = (value << 8) | lane;
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}
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tegra_sor_writel(sor, value, SOR_DP_TPG);
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err = tegra_sor_dp_train_fast(sor, &link);
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if (err < 0)
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dev_err(sor->dev, "DP fast link training failed: %d\n", err);
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dev_dbg(sor->dev, "fast link training succeeded\n");
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err = tegra_sor_power_up(sor, 250);
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if (err < 0)
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dev_err(sor->dev, "failed to power up SOR: %d\n", err);
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