RISC-V SoC driver fixes for v6.9-rc3

A fix for the ccache driver which no longer probed after the PLIC driver
 was converted to a platform driver. The JH7100 SoC depends on this
 driver to provide cache management ops that must be registered with an
 arch_initcall, so the ccache driver is partly converted to a platform
 driver, registering only the cache management ops with the initcall and
 the debug/edac register provision features of the driver as a platform
 driver.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZhEeLQAKCRB4tDGHoIJi
 0jdgAP0X6EECKhObfIXHP7uJFafYQA5UKBOgNZrA/N/VXxCDiQEAhZOz/2bq0EZu
 RN8ZIjF+bV9yDPulcS9IHMJlLNw/RQg=
 =F2ys
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmYVUQEACgkQYKtH/8kJ
 UidY/BAAjmX79pSrujbZ0lwru9qqA4TYLbNq2Uy0CrEAadYWZXlmRKIRcNYVxi8U
 kUCPycJ5H1nnIKtuVTqn6albpRvtIUUAqfNwBzABNPyrnAYumCYPmCvyCgO04WxG
 alHEfaf7fRG+6M7Il1G4xTf6NXsdEGE96V+E0TFPfqlyQGpoVarUlydyTFyoCvDG
 FMNAdQkGWm5oJFGTroe5XqP/XHtgJ+oOArWqdSn5cA5Hly/L3vGhsC2O6FEw4LQm
 GC+GKCGN85oURHM7qLzSY1PP1toUMIfU2Mh1TA9k2BvSmye9xHY+L5iyAga6qr3h
 ff4hWWu0QTiJfqOU0DjuOARAiSocBgPEg66tSs0q/jcOZCNjm3Hxq5HMx10bDfes
 3TskcxeDsMLlqIxEnJXrzzSrDfpqJARBjvoYB3AOaLthxPGcv9StYlJYRAaFLG3Y
 d4NyNWTahBGu5HA1Z7Vzql44F9OG6Kiw/mDYUgu8kqKc/hN6Z56tjm5zSZFD/fn/
 aKQ6fxuf1Ed7hK3UT2Iq7RJtB/aMXTpq5MmsNEf3s/5bpCUe8369kuc6O4HDJ2jZ
 nlH7iwg80bLIgYcaaBGo0rydlP/KPzHDJQLMJzBuyfz0jsJhkXW5HZTblUOIxvIA
 0ql5STW2pNFspUOR0gcR0YVPxwh2Gub0ZLQw7ISEzh6BpWpZdps=
 =PJbD
 -----END PGP SIGNATURE-----

Merge tag 'riscv-soc-fixes-for-v6.9-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes

RISC-V SoC driver fixes for v6.9-rc3

A fix for the ccache driver which no longer probed after the PLIC driver
was converted to a platform driver. The JH7100 SoC depends on this
driver to provide cache management ops that must be registered with an
arch_initcall, so the ccache driver is partly converted to a platform
driver, registering only the cache management ops with the initcall and
the debug/edac register provision features of the driver as a platform
driver.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-soc-fixes-for-v6.9-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  cache: sifive_ccache: Partially convert to a platform driver

Link: https://lore.kernel.org/r/20240406-botch-disband-efc69b8236be@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-04-09 16:30:24 +02:00
commit 01a71af381

View File

@ -15,6 +15,8 @@
#include <linux/of_address.h>
#include <linux/device.h>
#include <linux/bitfield.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <asm/cacheflush.h>
#include <asm/cacheinfo.h>
#include <asm/dma-noncoherent.h>
@ -247,13 +249,49 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
return IRQ_HANDLED;
}
static int sifive_ccache_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
unsigned long quirks;
int intr_num, rc;
quirks = (unsigned long)device_get_match_data(dev);
intr_num = platform_irq_count(pdev);
if (!intr_num)
return dev_err_probe(dev, -ENODEV, "No interrupts property\n");
for (int i = 0; i < intr_num; i++) {
if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR))
continue;
g_irq[i] = platform_get_irq(pdev, i);
if (g_irq[i] < 0)
return g_irq[i];
rc = devm_request_irq(dev, g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
if (rc)
return dev_err_probe(dev, rc, "Could not request IRQ %d\n", g_irq[i]);
}
return 0;
}
static struct platform_driver sifive_ccache_driver = {
.probe = sifive_ccache_probe,
.driver = {
.name = "sifive_ccache",
.of_match_table = sifive_ccache_ids,
},
};
static int __init sifive_ccache_init(void)
{
struct device_node *np;
struct resource res;
int i, rc, intr_num;
const struct of_device_id *match;
unsigned long quirks;
int rc;
np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
if (!np)
@ -277,28 +315,6 @@ static int __init sifive_ccache_init(void)
goto err_unmap;
}
intr_num = of_property_count_u32_elems(np, "interrupts");
if (!intr_num) {
pr_err("No interrupts property\n");
rc = -ENODEV;
goto err_unmap;
}
for (i = 0; i < intr_num; i++) {
g_irq[i] = irq_of_parse_and_map(np, i);
if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR))
continue;
rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
NULL);
if (rc) {
pr_err("Could not request IRQ %d\n", g_irq[i]);
goto err_free_irq;
}
}
of_node_put(np);
#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) {
riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
@ -315,11 +331,15 @@ static int __init sifive_ccache_init(void)
#ifdef CONFIG_DEBUG_FS
setup_sifive_debug();
#endif
rc = platform_driver_register(&sifive_ccache_driver);
if (rc)
goto err_unmap;
of_node_put(np);
return 0;
err_free_irq:
while (--i >= 0)
free_irq(g_irq[i], NULL);
err_unmap:
iounmap(ccache_base);
err_node_put: