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RISC-V SoC driver fixes for v6.9-rc3
A fix for the ccache driver which no longer probed after the PLIC driver was converted to a platform driver. The JH7100 SoC depends on this driver to provide cache management ops that must be registered with an arch_initcall, so the ccache driver is partly converted to a platform driver, registering only the cache management ops with the initcall and the debug/edac register provision features of the driver as a platform driver. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZhEeLQAKCRB4tDGHoIJi 0jdgAP0X6EECKhObfIXHP7uJFafYQA5UKBOgNZrA/N/VXxCDiQEAhZOz/2bq0EZu RN8ZIjF+bV9yDPulcS9IHMJlLNw/RQg= =F2ys -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmYVUQEACgkQYKtH/8kJ UidY/BAAjmX79pSrujbZ0lwru9qqA4TYLbNq2Uy0CrEAadYWZXlmRKIRcNYVxi8U kUCPycJ5H1nnIKtuVTqn6albpRvtIUUAqfNwBzABNPyrnAYumCYPmCvyCgO04WxG alHEfaf7fRG+6M7Il1G4xTf6NXsdEGE96V+E0TFPfqlyQGpoVarUlydyTFyoCvDG FMNAdQkGWm5oJFGTroe5XqP/XHtgJ+oOArWqdSn5cA5Hly/L3vGhsC2O6FEw4LQm GC+GKCGN85oURHM7qLzSY1PP1toUMIfU2Mh1TA9k2BvSmye9xHY+L5iyAga6qr3h ff4hWWu0QTiJfqOU0DjuOARAiSocBgPEg66tSs0q/jcOZCNjm3Hxq5HMx10bDfes 3TskcxeDsMLlqIxEnJXrzzSrDfpqJARBjvoYB3AOaLthxPGcv9StYlJYRAaFLG3Y d4NyNWTahBGu5HA1Z7Vzql44F9OG6Kiw/mDYUgu8kqKc/hN6Z56tjm5zSZFD/fn/ aKQ6fxuf1Ed7hK3UT2Iq7RJtB/aMXTpq5MmsNEf3s/5bpCUe8369kuc6O4HDJ2jZ nlH7iwg80bLIgYcaaBGo0rydlP/KPzHDJQLMJzBuyfz0jsJhkXW5HZTblUOIxvIA 0ql5STW2pNFspUOR0gcR0YVPxwh2Gub0ZLQw7ISEzh6BpWpZdps= =PJbD -----END PGP SIGNATURE----- Merge tag 'riscv-soc-fixes-for-v6.9-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes RISC-V SoC driver fixes for v6.9-rc3 A fix for the ccache driver which no longer probed after the PLIC driver was converted to a platform driver. The JH7100 SoC depends on this driver to provide cache management ops that must be registered with an arch_initcall, so the ccache driver is partly converted to a platform driver, registering only the cache management ops with the initcall and the debug/edac register provision features of the driver as a platform driver. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-fixes-for-v6.9-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: cache: sifive_ccache: Partially convert to a platform driver Link: https://lore.kernel.org/r/20240406-botch-disband-efc69b8236be@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
01a71af381
72
drivers/cache/sifive_ccache.c
vendored
72
drivers/cache/sifive_ccache.c
vendored
@ -15,6 +15,8 @@
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#include <linux/of_address.h>
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#include <linux/device.h>
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#include <linux/bitfield.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <asm/cacheflush.h>
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#include <asm/cacheinfo.h>
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#include <asm/dma-noncoherent.h>
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@ -247,13 +249,49 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
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return IRQ_HANDLED;
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}
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static int sifive_ccache_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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unsigned long quirks;
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int intr_num, rc;
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quirks = (unsigned long)device_get_match_data(dev);
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intr_num = platform_irq_count(pdev);
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if (!intr_num)
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return dev_err_probe(dev, -ENODEV, "No interrupts property\n");
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for (int i = 0; i < intr_num; i++) {
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if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR))
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continue;
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g_irq[i] = platform_get_irq(pdev, i);
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if (g_irq[i] < 0)
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return g_irq[i];
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rc = devm_request_irq(dev, g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
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if (rc)
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return dev_err_probe(dev, rc, "Could not request IRQ %d\n", g_irq[i]);
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}
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return 0;
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}
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static struct platform_driver sifive_ccache_driver = {
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.probe = sifive_ccache_probe,
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.driver = {
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.name = "sifive_ccache",
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.of_match_table = sifive_ccache_ids,
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},
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};
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static int __init sifive_ccache_init(void)
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{
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struct device_node *np;
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struct resource res;
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int i, rc, intr_num;
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const struct of_device_id *match;
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unsigned long quirks;
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int rc;
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np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
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if (!np)
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@ -277,28 +315,6 @@ static int __init sifive_ccache_init(void)
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goto err_unmap;
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}
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intr_num = of_property_count_u32_elems(np, "interrupts");
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if (!intr_num) {
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pr_err("No interrupts property\n");
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rc = -ENODEV;
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goto err_unmap;
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}
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for (i = 0; i < intr_num; i++) {
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g_irq[i] = irq_of_parse_and_map(np, i);
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if (i == DATA_UNCORR && (quirks & QUIRK_BROKEN_DATA_UNCORR))
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continue;
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rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
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NULL);
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if (rc) {
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pr_err("Could not request IRQ %d\n", g_irq[i]);
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goto err_free_irq;
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}
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}
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of_node_put(np);
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#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
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if (quirks & QUIRK_NONSTANDARD_CACHE_OPS) {
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riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
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@ -315,11 +331,15 @@ static int __init sifive_ccache_init(void)
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#ifdef CONFIG_DEBUG_FS
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setup_sifive_debug();
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#endif
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rc = platform_driver_register(&sifive_ccache_driver);
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if (rc)
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goto err_unmap;
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of_node_put(np);
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return 0;
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err_free_irq:
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while (--i >= 0)
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free_irq(g_irq[i], NULL);
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err_unmap:
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iounmap(ccache_base);
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err_node_put:
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