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ASoC: Fix WM9081 PowerPC compiler issues
Ensure that we always set a new sysclk when using the FLL in master mode and pick out the correct value for the sample rate in hw_params(). Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -702,9 +702,10 @@ static int configure_clock(struct snd_soc_codec *codec)
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* performance. */
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for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
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target = wm9081->fs * clk_sys_rates[i].ratio;
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new_sysclk = target;
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if (target >= wm9081->bclk &&
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target > 3000000)
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new_sysclk = target;
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break;
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}
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} else if (wm9081->fs) {
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for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
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@ -1102,7 +1103,8 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
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}
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dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
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sample_rates[best].rate);
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clk_ctrl2 |= (sample_rates[i].sample_rate << WM9081_SAMPLE_RATE_SHIFT);
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clk_ctrl2 |= (sample_rates[best].sample_rate
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<< WM9081_SAMPLE_RATE_SHIFT);
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/* BCLK_DIV */
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best = 0;
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