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nfp: standardize FW header whitespace
The nfp_net_ctrl.h file used spaces for indentation in the past but tabs have crept in. Host driver files use tabs for indentation by default, so let's convert to tabs for consistency across the file and our drivers. Signed-off-by: Michael Rapson <michael.rapson@netronome.com> Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Rapson
David S. Miller
parent
4a8864822d
commit
014f900898
@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2015-2017 Netronome Systems, Inc.
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* Copyright (C) 2015-2018 Netronome Systems, Inc.
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*
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* This software is dual licensed under the GNU General License Version 2,
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* June 1991 as shown in the file COPYING in the top-level directory of this
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@ -51,12 +51,12 @@
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* The configuration BAR is 8K in size, but due to
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* THB-350, 32k needs to be reserved.
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*/
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#define NFP_NET_CFG_BAR_SZ (32 * 1024)
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#define NFP_NET_CFG_BAR_SZ (32 * 1024)
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/**
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* Offset in Freelist buffer where packet starts on RX
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*/
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#define NFP_NET_RX_OFFSET 32
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#define NFP_NET_RX_OFFSET 32
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/**
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* LSO parameters
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@ -75,65 +75,65 @@
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#define NFP_NET_META_PORTID 5
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#define NFP_NET_META_CSUM 6 /* checksum complete type */
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#define NFP_META_PORT_ID_CTRL ~0U
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#define NFP_META_PORT_ID_CTRL ~0U
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/**
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* Hash type pre-pended when a RSS hash was computed
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*/
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#define NFP_NET_RSS_NONE 0
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#define NFP_NET_RSS_IPV4 1
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#define NFP_NET_RSS_IPV6 2
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#define NFP_NET_RSS_IPV6_EX 3
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#define NFP_NET_RSS_IPV4_TCP 4
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#define NFP_NET_RSS_IPV6_TCP 5
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#define NFP_NET_RSS_IPV6_EX_TCP 6
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#define NFP_NET_RSS_IPV4_UDP 7
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#define NFP_NET_RSS_IPV6_UDP 8
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#define NFP_NET_RSS_IPV6_EX_UDP 9
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#define NFP_NET_RSS_NONE 0
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#define NFP_NET_RSS_IPV4 1
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#define NFP_NET_RSS_IPV6 2
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#define NFP_NET_RSS_IPV6_EX 3
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#define NFP_NET_RSS_IPV4_TCP 4
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#define NFP_NET_RSS_IPV6_TCP 5
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#define NFP_NET_RSS_IPV6_EX_TCP 6
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#define NFP_NET_RSS_IPV4_UDP 7
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#define NFP_NET_RSS_IPV6_UDP 8
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#define NFP_NET_RSS_IPV6_EX_UDP 9
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/**
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* Ring counts
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* %NFP_NET_TXR_MAX: Maximum number of TX rings
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* %NFP_NET_RXR_MAX: Maximum number of RX rings
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* %NFP_NET_TXR_MAX: Maximum number of TX rings
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* %NFP_NET_RXR_MAX: Maximum number of RX rings
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*/
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#define NFP_NET_TXR_MAX 64
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#define NFP_NET_RXR_MAX 64
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#define NFP_NET_TXR_MAX 64
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#define NFP_NET_RXR_MAX 64
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/**
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* Read/Write config words (0x0000 - 0x002c)
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* %NFP_NET_CFG_CTRL: Global control
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* %NFP_NET_CFG_CTRL: Global control
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* %NFP_NET_CFG_UPDATE: Indicate which fields are updated
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* %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
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* %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
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* %NFP_NET_CFG_MTU: Set MTU size
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* %NFP_NET_CFG_MTU: Set MTU size
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* %NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU)
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* %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
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* %NFP_NET_CFG_LSC: MSI-X table entry for link state changes
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* %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
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* %NFP_NET_CFG_LSC: MSI-X table entry for link state changes
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* %NFP_NET_CFG_MACADDR: MAC address
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*
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* TODO:
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* - define Error details in UPDATE
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*/
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#define NFP_NET_CFG_CTRL 0x0000
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#define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */
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#define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */
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#define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */
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#define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */
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#define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */
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#define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */
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#define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */
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#define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */
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#define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */
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#define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */
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#define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO (version 1) */
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#define NFP_NET_CFG_CTRL 0x0000
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#define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */
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#define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */
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#define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */
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#define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */
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#define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */
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#define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */
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#define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */
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#define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */
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#define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */
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#define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */
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#define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO (version 1) */
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#define NFP_NET_CFG_CTRL_CTAG_FILTER (0x1 << 11) /* VLAN CTAG filtering */
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#define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */
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#define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */
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#define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS (version 1) */
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#define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */
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#define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */
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#define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */
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#define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/
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#define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */
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#define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */
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#define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */
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#define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */
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#define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/
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#define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */
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#define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */
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#define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* VXLAN tunnel support */
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#define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* NVGRE tunnel support */
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@ -152,35 +152,35 @@
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#define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \
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NFP_NET_CFG_CTRL_CSUM_COMPLETE)
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#define NFP_NET_CFG_UPDATE 0x0004
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#define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */
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#define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */
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#define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */
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#define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */
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#define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */
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#define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */
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#define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */
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#define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */
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#define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */
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#define NFP_NET_CFG_UPDATE 0x0004
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#define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */
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#define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */
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#define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */
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#define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */
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#define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */
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#define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */
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#define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */
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#define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */
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#define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */
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#define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */
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#define NFP_NET_CFG_UPDATE_BPF (0x1 << 10) /* BPF program load */
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#define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */
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#define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */
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#define NFP_NET_CFG_UPDATE_VF (0x1 << 13) /* VF settings change */
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#define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */
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#define NFP_NET_CFG_TXRS_ENABLE 0x0008
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#define NFP_NET_CFG_RXRS_ENABLE 0x0010
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#define NFP_NET_CFG_MTU 0x0018
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#define NFP_NET_CFG_FLBUFSZ 0x001c
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#define NFP_NET_CFG_EXN 0x001f
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#define NFP_NET_CFG_LSC 0x0020
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#define NFP_NET_CFG_MACADDR 0x0024
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#define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */
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#define NFP_NET_CFG_TXRS_ENABLE 0x0008
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#define NFP_NET_CFG_RXRS_ENABLE 0x0010
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#define NFP_NET_CFG_MTU 0x0018
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#define NFP_NET_CFG_FLBUFSZ 0x001c
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#define NFP_NET_CFG_EXN 0x001f
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#define NFP_NET_CFG_LSC 0x0020
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#define NFP_NET_CFG_MACADDR 0x0024
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/**
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* Read-only words (0x0030 - 0x0050):
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* %NFP_NET_CFG_VERSION: Firmware version number
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* %NFP_NET_CFG_STS: Status
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* %NFP_NET_CFG_CAP: Capabilities (same bits as %NFP_NET_CFG_CTRL)
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* %NFP_NET_CFG_STS: Status
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* %NFP_NET_CFG_CAP: Capabilities (same bits as %NFP_NET_CFG_CTRL)
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* %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings
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* %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings
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* %NFP_NET_CFG_MAX_MTU: Maximum support MTU
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@ -190,37 +190,37 @@
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* TODO:
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* - define more STS bits
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*/
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#define NFP_NET_CFG_VERSION 0x0030
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#define NFP_NET_CFG_VERSION 0x0030
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#define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24)
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#define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16)
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#define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16)
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#define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16)
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#define NFP_NET_CFG_VERSION_CLASS_GENERIC 0
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#define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8)
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#define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8)
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#define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8)
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#define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0)
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#define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0)
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#define NFP_NET_CFG_STS 0x0034
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#define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */
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#define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0)
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#define NFP_NET_CFG_STS 0x0034
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#define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */
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/* Link rate */
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#define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1
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#define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF
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#define NFP_NET_CFG_STS_LINK_RATE \
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#define NFP_NET_CFG_STS_LINK_RATE \
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(NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT)
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#define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0
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#define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1
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#define NFP_NET_CFG_STS_LINK_RATE_1G 2
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#define NFP_NET_CFG_STS_LINK_RATE_10G 3
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#define NFP_NET_CFG_STS_LINK_RATE_25G 4
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#define NFP_NET_CFG_STS_LINK_RATE_40G 5
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#define NFP_NET_CFG_STS_LINK_RATE_50G 6
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#define NFP_NET_CFG_STS_LINK_RATE_100G 7
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#define NFP_NET_CFG_CAP 0x0038
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#define NFP_NET_CFG_MAX_TXRINGS 0x003c
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#define NFP_NET_CFG_MAX_RXRINGS 0x0040
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#define NFP_NET_CFG_MAX_MTU 0x0044
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#define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1
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#define NFP_NET_CFG_STS_LINK_RATE_1G 2
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#define NFP_NET_CFG_STS_LINK_RATE_10G 3
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#define NFP_NET_CFG_STS_LINK_RATE_25G 4
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#define NFP_NET_CFG_STS_LINK_RATE_40G 5
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#define NFP_NET_CFG_STS_LINK_RATE_50G 6
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#define NFP_NET_CFG_STS_LINK_RATE_100G 7
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#define NFP_NET_CFG_CAP 0x0038
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#define NFP_NET_CFG_MAX_TXRINGS 0x003c
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#define NFP_NET_CFG_MAX_RXRINGS 0x0040
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#define NFP_NET_CFG_MAX_MTU 0x0044
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/* Next two words are being used by VFs for solving THB350 issue */
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#define NFP_NET_CFG_START_TXQ 0x0048
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#define NFP_NET_CFG_START_RXQ 0x004c
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#define NFP_NET_CFG_START_TXQ 0x0048
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#define NFP_NET_CFG_START_RXQ 0x004c
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/**
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* Prepend configuration
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@ -280,8 +280,8 @@
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/**
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* 40B reserved for future use (0x0098 - 0x00c0)
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*/
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#define NFP_NET_CFG_RESERVED 0x0098
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#define NFP_NET_CFG_RESERVED_SZ 0x0028
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#define NFP_NET_CFG_RESERVED 0x0098
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#define NFP_NET_CFG_RESERVED_SZ 0x0028
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/**
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* RSS configuration (0x0100 - 0x01ac):
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@ -290,26 +290,26 @@
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* %NFP_NET_CFG_RSS_KEY: RSS "secret" key
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* %NFP_NET_CFG_RSS_ITBL: RSS indirection table
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*/
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#define NFP_NET_CFG_RSS_BASE 0x0100
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#define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE
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#define NFP_NET_CFG_RSS_MASK (0x7f)
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#define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f)
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#define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */
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#define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */
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#define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */
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#define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */
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#define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */
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#define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */
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#define NFP_NET_CFG_RSS_BASE 0x0100
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#define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE
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#define NFP_NET_CFG_RSS_MASK (0x7f)
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#define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f)
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#define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */
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#define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */
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#define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */
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#define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */
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#define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */
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#define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */
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#define NFP_NET_CFG_RSS_HFUNC 0xff000000
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#define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */
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#define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */
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#define NFP_NET_CFG_RSS_XOR (1 << 25) /* Use XOR as hash */
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#define NFP_NET_CFG_RSS_CRC32 (1 << 26) /* Use CRC32 as hash */
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#define NFP_NET_CFG_RSS_HFUNCS 3
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#define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4)
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#define NFP_NET_CFG_RSS_KEY_SZ 0x28
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#define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \
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#define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4)
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#define NFP_NET_CFG_RSS_KEY_SZ 0x28
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#define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \
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NFP_NET_CFG_RSS_KEY_SZ)
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#define NFP_NET_CFG_RSS_ITBL_SZ 0x80
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#define NFP_NET_CFG_RSS_ITBL_SZ 0x80
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/**
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* TX ring configuration (0x200 - 0x800)
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@ -321,13 +321,13 @@
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* %NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries)
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* %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet
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*/
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#define NFP_NET_CFG_TXR_BASE 0x0200
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#define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
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#define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \
|
||||
#define NFP_NET_CFG_TXR_BASE 0x0200
|
||||
#define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
|
||||
#define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \
|
||||
((_x) * 0x8))
|
||||
#define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
|
||||
#define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
|
||||
#define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
|
||||
#define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
|
||||
#define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
|
||||
#define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
|
||||
#define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \
|
||||
((_x) * 0x4))
|
||||
|
||||
@ -340,11 +340,11 @@
|
||||
* %NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries)
|
||||
* %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries)
|
||||
*/
|
||||
#define NFP_NET_CFG_RXR_BASE 0x0800
|
||||
#define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
|
||||
#define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
|
||||
#define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
|
||||
#define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
|
||||
#define NFP_NET_CFG_RXR_BASE 0x0800
|
||||
#define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
|
||||
#define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
|
||||
#define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
|
||||
#define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
|
||||
#define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \
|
||||
((_x) * 0x4))
|
||||
|
||||
@ -358,36 +358,36 @@
|
||||
* the MSI-X entry and the host driver must clear the register to
|
||||
* re-enable the interrupt.
|
||||
*/
|
||||
#define NFP_NET_CFG_ICR_BASE 0x0c00
|
||||
#define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x))
|
||||
#define NFP_NET_CFG_ICR_UNMASKED 0x0
|
||||
#define NFP_NET_CFG_ICR_RXTX 0x1
|
||||
#define NFP_NET_CFG_ICR_LSC 0x2
|
||||
#define NFP_NET_CFG_ICR_BASE 0x0c00
|
||||
#define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x))
|
||||
#define NFP_NET_CFG_ICR_UNMASKED 0x0
|
||||
#define NFP_NET_CFG_ICR_RXTX 0x1
|
||||
#define NFP_NET_CFG_ICR_LSC 0x2
|
||||
|
||||
/**
|
||||
* General device stats (0x0d00 - 0x0d90)
|
||||
* all counters are 64bit.
|
||||
*/
|
||||
#define NFP_NET_CFG_STATS_BASE 0x0d00
|
||||
#define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00)
|
||||
#define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08)
|
||||
#define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10)
|
||||
#define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18)
|
||||
#define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20)
|
||||
#define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28)
|
||||
#define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30)
|
||||
#define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38)
|
||||
#define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40)
|
||||
#define NFP_NET_CFG_STATS_BASE 0x0d00
|
||||
#define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00)
|
||||
#define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08)
|
||||
#define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10)
|
||||
#define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18)
|
||||
#define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20)
|
||||
#define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28)
|
||||
#define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30)
|
||||
#define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38)
|
||||
#define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40)
|
||||
|
||||
#define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48)
|
||||
#define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50)
|
||||
#define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58)
|
||||
#define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60)
|
||||
#define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68)
|
||||
#define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70)
|
||||
#define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78)
|
||||
#define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80)
|
||||
#define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88)
|
||||
#define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48)
|
||||
#define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50)
|
||||
#define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58)
|
||||
#define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60)
|
||||
#define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68)
|
||||
#define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70)
|
||||
#define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78)
|
||||
#define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80)
|
||||
#define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88)
|
||||
|
||||
#define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90)
|
||||
#define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98)
|
||||
@ -404,11 +404,11 @@
|
||||
* %NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count)
|
||||
* %NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count)
|
||||
*/
|
||||
#define NFP_NET_CFG_TXR_STATS_BASE 0x1000
|
||||
#define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \
|
||||
#define NFP_NET_CFG_TXR_STATS_BASE 0x1000
|
||||
#define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \
|
||||
((_x) * 0x10))
|
||||
#define NFP_NET_CFG_RXR_STATS_BASE 0x1400
|
||||
#define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \
|
||||
#define NFP_NET_CFG_RXR_STATS_BASE 0x1400
|
||||
#define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \
|
||||
((_x) * 0x10))
|
||||
|
||||
/**
|
||||
@ -444,7 +444,7 @@
|
||||
* %NFP_NET_CFG_TLV_TYPE: Offset of type within the TLV
|
||||
* %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV
|
||||
* %NFP_NET_CFG_TLV_LENGTH: Offset of length within the TLV
|
||||
* %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments
|
||||
* %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments
|
||||
* %NFP_NET_CFG_TLV_VALUE: Offset of value with the TLV
|
||||
*
|
||||
* List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE.
|
||||
@ -457,12 +457,12 @@
|
||||
* Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH.
|
||||
*/
|
||||
#define NFP_NET_CFG_TLV_TYPE 0x00
|
||||
#define NFP_NET_CFG_TLV_TYPE_REQUIRED 0x8000
|
||||
#define NFP_NET_CFG_TLV_TYPE_REQUIRED 0x8000
|
||||
#define NFP_NET_CFG_TLV_LENGTH 0x02
|
||||
#define NFP_NET_CFG_TLV_LENGTH_INC 4
|
||||
#define NFP_NET_CFG_TLV_VALUE 0x04
|
||||
|
||||
#define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000
|
||||
#define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000
|
||||
#define NFP_NET_CFG_TLV_HEADER_TYPE 0x7fff0000
|
||||
#define NFP_NET_CFG_TLV_HEADER_LENGTH 0x0000ffff
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user