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ARM: SoC non-urgent fixes for v4.3

Browse Source 
We normally collect non-urgent fixes during the release cycle and queue
 them for the merge window.
 
 This time around the list is short (in part because some have gone in other
 branches).
 
 - Maintainers addition for bcm2835
 - IRQ number fix for orion5x (been present since 3.18)
 - DT fix for display on exynos3250
 - Exynos fix to use of IOMEM_ERR_PTR properly
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Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-urgent fixes from Olof Johansson:
 "We normally collect non-urgent fixes during the release cycle and
  queue them for the merge window.

  This time around the list is short (in part because some have gone in
  other branches).

   - Maintainers addition for bcm2835
   - IRQ number fix for orion5x (been present since 3.18)
   - DT fix for display on exynos3250
   - Exynos fix to use of IOMEM_ERR_PTR properly"

* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: orion5x: fix legacy orion5x IRQ numbers
  MAINTAINERS: Explicitly add linux-arm-kernel for bcm2835
  MAINTAINERS: Add myself as a bcm2835 co-maintainer.
  ARM: EXYNOS: Use IOMEM_ERR_PTR when function returns iomem
  ARM: dts: fix clock-frequency of display timing0 for exynos3250-rinato
This commit is contained in:
Linus Torvalds 2015-09-01 12:01:40 -07:00
commit 00e3fcc221
6 changed files with 39 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -2224,7 +2224,9 @@ F: drivers/clocksource/bcm_kona_timer.c
BROADCOM BCM2835 ARM ARCHITECTURE BROADCOM BCM2835 ARM ARCHITECTURE
M: Stephen Warren <swarren@wwwdotorg.org> M: Stephen Warren <swarren@wwwdotorg.org>
M: Lee Jones <lee@kernel.org> M: Lee Jones <lee@kernel.org>
M: Eric Anholt <eric@anholt.net>
L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi.git
S: Maintained S: Maintained
N: bcm2835 N: bcm2835

1
arch/arm/Kconfig
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@ -536,6 +536,7 @@ config ARCH_ORION5X
select MVEBU_MBUS select MVEBU_MBUS
select PCI select PCI
select PLAT_ORION_LEGACY select PLAT_ORION_LEGACY
select MULTI_IRQ_HANDLER
help help
Support for the following Marvell Orion 5x series SoCs: Support for the following Marvell Orion 5x series SoCs:
Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),

2
arch/arm/boot/dts/exynos3250-rinato.dts
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@ -182,7 +182,7 @@
display-timings { display-timings {
timing-0 { timing-0 {
clock-frequency = <0>; clock-frequency = <4600000>;
hactive = <320>; hactive = <320>;
vactive = <320>; vactive = <320>;
hfront-porch = <1>; hfront-porch = <1>;

2
arch/arm/mach-exynos/platsmp.c
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@ -182,7 +182,7 @@ static inline void __iomem *cpu_boot_reg(int cpu)
boot_reg = cpu_boot_reg_base(); boot_reg = cpu_boot_reg_base();
if (!boot_reg) if (!boot_reg)
return ERR_PTR(-ENODEV); return IOMEM_ERR_PTR(-ENODEV);
if (soc_is_exynos4412()) if (soc_is_exynos4412())
boot_reg += 4*cpu; boot_reg += 4*cpu;
else if (soc_is_exynos5420() || soc_is_exynos5800()) else if (soc_is_exynos5420() || soc_is_exynos5800())

64
arch/arm/mach-orion5x/include/mach/irqs.h
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@ -16,42 +16,42 @@
/* /*
* Orion Main Interrupt Controller * Orion Main Interrupt Controller
*/ */
#define IRQ_ORION5X_BRIDGE 0 #define IRQ_ORION5X_BRIDGE (1 + 0)
#define IRQ_ORION5X_DOORBELL_H2C 1 #define IRQ_ORION5X_DOORBELL_H2C (1 + 1)
#define IRQ_ORION5X_DOORBELL_C2H 2 #define IRQ_ORION5X_DOORBELL_C2H (1 + 2)
#define IRQ_ORION5X_UART0 3 #define IRQ_ORION5X_UART0 (1 + 3)
#define IRQ_ORION5X_UART1 4 #define IRQ_ORION5X_UART1 (1 + 4)
#define IRQ_ORION5X_I2C 5 #define IRQ_ORION5X_I2C (1 + 5)
#define IRQ_ORION5X_GPIO_0_7 6 #define IRQ_ORION5X_GPIO_0_7 (1 + 6)
#define IRQ_ORION5X_GPIO_8_15 7 #define IRQ_ORION5X_GPIO_8_15 (1 + 7)
#define IRQ_ORION5X_GPIO_16_23 8 #define IRQ_ORION5X_GPIO_16_23 (1 + 8)
#define IRQ_ORION5X_GPIO_24_31 9 #define IRQ_ORION5X_GPIO_24_31 (1 + 9)
#define IRQ_ORION5X_PCIE0_ERR 10 #define IRQ_ORION5X_PCIE0_ERR (1 + 10)
#define IRQ_ORION5X_PCIE0_INT 11 #define IRQ_ORION5X_PCIE0_INT (1 + 11)
#define IRQ_ORION5X_USB1_CTRL 12 #define IRQ_ORION5X_USB1_CTRL (1 + 12)
#define IRQ_ORION5X_DEV_BUS_ERR 14 #define IRQ_ORION5X_DEV_BUS_ERR (1 + 14)
#define IRQ_ORION5X_PCI_ERR 15 #define IRQ_ORION5X_PCI_ERR (1 + 15)
#define IRQ_ORION5X_USB_BR_ERR 16 #define IRQ_ORION5X_USB_BR_ERR (1 + 16)
#define IRQ_ORION5X_USB0_CTRL 17 #define IRQ_ORION5X_USB0_CTRL (1 + 17)
#define IRQ_ORION5X_ETH_RX 18 #define IRQ_ORION5X_ETH_RX (1 + 18)
#define IRQ_ORION5X_ETH_TX 19 #define IRQ_ORION5X_ETH_TX (1 + 19)
#define IRQ_ORION5X_ETH_MISC 20 #define IRQ_ORION5X_ETH_MISC (1 + 20)
#define IRQ_ORION5X_ETH_SUM 21 #define IRQ_ORION5X_ETH_SUM (1 + 21)
#define IRQ_ORION5X_ETH_ERR 22 #define IRQ_ORION5X_ETH_ERR (1 + 22)
#define IRQ_ORION5X_IDMA_ERR 23 #define IRQ_ORION5X_IDMA_ERR (1 + 23)
#define IRQ_ORION5X_IDMA_0 24 #define IRQ_ORION5X_IDMA_0 (1 + 24)
#define IRQ_ORION5X_IDMA_1 25 #define IRQ_ORION5X_IDMA_1 (1 + 25)
#define IRQ_ORION5X_IDMA_2 26 #define IRQ_ORION5X_IDMA_2 (1 + 26)
#define IRQ_ORION5X_IDMA_3 27 #define IRQ_ORION5X_IDMA_3 (1 + 27)
#define IRQ_ORION5X_CESA 28 #define IRQ_ORION5X_CESA (1 + 28)
#define IRQ_ORION5X_SATA 29 #define IRQ_ORION5X_SATA (1 + 29)
#define IRQ_ORION5X_XOR0 30 #define IRQ_ORION5X_XOR0 (1 + 30)
#define IRQ_ORION5X_XOR1 31 #define IRQ_ORION5X_XOR1 (1 + 31)
/* /*
* Orion General Purpose Pins * Orion General Purpose Pins
*/ */
#define IRQ_ORION5X_GPIO_START 32 #define IRQ_ORION5X_GPIO_START 33
#define NR_GPIO_IRQS 32 #define NR_GPIO_IRQS 32
#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) #define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)

4
arch/arm/mach-orion5x/irq.c
View File

@ -42,7 +42,7 @@ __exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
stat = readl_relaxed(MAIN_IRQ_CAUSE); stat = readl_relaxed(MAIN_IRQ_CAUSE);
stat &= readl_relaxed(MAIN_IRQ_MASK); stat &= readl_relaxed(MAIN_IRQ_MASK);
if (stat) { if (stat) {
unsigned int hwirq = __fls(stat); unsigned int hwirq = 1 + __fls(stat);
handle_IRQ(hwirq, regs); handle_IRQ(hwirq, regs);
return; return;
} }
@ -51,7 +51,7 @@ __exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
void __init orion5x_init_irq(void) void __init orion5x_init_irq(void)
{ {
orion_irq_init(0, MAIN_IRQ_MASK); orion_irq_init(1, MAIN_IRQ_MASK);
#ifdef CONFIG_MULTI_IRQ_HANDLER #ifdef CONFIG_MULTI_IRQ_HANDLER
set_handle_irq(orion5x_legacy_handle_irq); set_handle_irq(orion5x_legacy_handle_irq);