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media: atomisp: Drop ia_css_debug_dump_debug_info() and functions only used by it

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ia_css_debug_dump_debug_info() is defined but never called anywhere,
drop it.

Also drop all the other ia_css_debug_dump_* functions only called by
ia_css_debug_dump_debug_info(), as well as *_get_state() functions only
used by those.

Link: https://lore.kernel.org/r/20230812133523.355581-1-hdegoede@redhat.com

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Hans de Goede 2023-08-12 15:35:22 +02:00 committed by Mauro Carvalho Chehab
parent 42c26b4cd1
commit 00c408775a
17 changed files with 0 additions and 2276 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

266
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma.c
View File

@ -23,272 +23,6 @@
#include "dma_private.h"
#endif /* __INLINE_DMA__ */
void dma_get_state(const dma_ID_t ID, dma_state_t *state)
{
int i;
hrt_data tmp;
assert(ID < N_DMA_ID);
assert(state);
tmp = dma_reg_load(ID, DMA_COMMAND_FSM_REG_IDX);
//reg [3:0] : flags error [3], stall, run, idle [0]
//reg [9:4] : command
//reg[14:10] : channel
//reg [23:15] : param
state->fsm_command_idle = tmp & 0x1;
state->fsm_command_run = tmp & 0x2;
state->fsm_command_stalling = tmp & 0x4;
state->fsm_command_error = tmp & 0x8;
state->last_command_channel = (tmp >> 10 & 0x1F);
state->last_command_param = (tmp >> 15 & 0x0F);
tmp = (tmp >> 4) & 0x3F;
/* state->last_command = (dma_commands_t)tmp; */
/* if the enumerator is made non-linear */
/* AM: the list below does not cover all the cases*/
/* and these are not correct */
/* therefore for just dumpinmg this command*/
state->last_command = tmp;
/*
if (tmp == 0)
state->last_command = DMA_COMMAND_READ;
if (tmp == 1)
state->last_command = DMA_COMMAND_WRITE;
if (tmp == 2)
state->last_command = DMA_COMMAND_SET_CHANNEL;
if (tmp == 3)
state->last_command = DMA_COMMAND_SET_PARAM;
if (tmp == 4)
state->last_command = DMA_COMMAND_READ_SPECIFIC;
if (tmp == 5)
state->last_command = DMA_COMMAND_WRITE_SPECIFIC;
if (tmp == 8)
state->last_command = DMA_COMMAND_INIT;
if (tmp == 12)
state->last_command = DMA_COMMAND_INIT_SPECIFIC;
if (tmp == 15)
state->last_command = DMA_COMMAND_RST;
*/
/* No sub-fields, idx = 0 */
state->current_command = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_CMD_IDX));
state->current_addr_a = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_A_IDX));
state->current_addr_b = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_B_IDX));
tmp = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_STATE_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_idle = tmp & 0x1;
state->fsm_ctrl_run = tmp & 0x2;
state->fsm_ctrl_stalling = tmp & 0x4;
state->fsm_ctrl_error = tmp & 0x8;
tmp = tmp >> 4;
/* state->fsm_ctrl_state = (dma_ctrl_states_t)tmp; */
if (tmp == 0)
state->fsm_ctrl_state = DMA_CTRL_STATE_IDLE;
if (tmp == 1)
state->fsm_ctrl_state = DMA_CTRL_STATE_REQ_RCV;
if (tmp == 2)
state->fsm_ctrl_state = DMA_CTRL_STATE_RCV;
if (tmp == 3)
state->fsm_ctrl_state = DMA_CTRL_STATE_RCV_REQ;
if (tmp == 4)
state->fsm_ctrl_state = DMA_CTRL_STATE_INIT;
state->fsm_ctrl_source_dev = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_source_addr = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_source_stride = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_source_width = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_source_height = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_pack_source_dev = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_pack_dest_dev = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_dest_addr = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_dest_stride = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_pack_source_width = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_pack_dest_height = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_pack_dest_width = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_pack_source_elems = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_pack_dest_elems = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
state->fsm_ctrl_pack_extension = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX,
_DMA_FSM_GROUP_FSM_CTRL_IDX));
tmp = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_PACK_STATE_IDX,
_DMA_FSM_GROUP_FSM_PACK_IDX));
state->pack_idle = tmp & 0x1;
state->pack_run = tmp & 0x2;
state->pack_stalling = tmp & 0x4;
state->pack_error = tmp & 0x8;
state->pack_cnt_height = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX,
_DMA_FSM_GROUP_FSM_PACK_IDX));
state->pack_src_cnt_width = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX,
_DMA_FSM_GROUP_FSM_PACK_IDX));
state->pack_dest_cnt_width = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX,
_DMA_FSM_GROUP_FSM_PACK_IDX));
tmp = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_REQ_STATE_IDX,
_DMA_FSM_GROUP_FSM_REQ_IDX));
/* state->read_state = (dma_rw_states_t)tmp; */
if (tmp == 0)
state->read_state = DMA_RW_STATE_IDLE;
if (tmp == 1)
state->read_state = DMA_RW_STATE_REQ;
if (tmp == 2)
state->read_state = DMA_RW_STATE_NEXT_LINE;
if (tmp == 3)
state->read_state = DMA_RW_STATE_UNLOCK_CHANNEL;
state->read_cnt_height = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX,
_DMA_FSM_GROUP_FSM_REQ_IDX));
state->read_cnt_width = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX,
_DMA_FSM_GROUP_FSM_REQ_IDX));
tmp = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_WR_STATE_IDX,
_DMA_FSM_GROUP_FSM_WR_IDX));
/* state->write_state = (dma_rw_states_t)tmp; */
if (tmp == 0)
state->write_state = DMA_RW_STATE_IDLE;
if (tmp == 1)
state->write_state = DMA_RW_STATE_REQ;
if (tmp == 2)
state->write_state = DMA_RW_STATE_NEXT_LINE;
if (tmp == 3)
state->write_state = DMA_RW_STATE_UNLOCK_CHANNEL;
state->write_height = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX,
_DMA_FSM_GROUP_FSM_WR_IDX));
state->write_width = dma_reg_load(ID,
DMA_CG_INFO_REG_IDX(
_DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX,
_DMA_FSM_GROUP_FSM_WR_IDX));
for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
dma_port_state_t *port = &state->port_states[i];
tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(0, i));
port->req_cs = ((tmp & 0x1) != 0);
port->req_we_n = ((tmp & 0x2) != 0);
port->req_run = ((tmp & 0x4) != 0);
port->req_ack = ((tmp & 0x8) != 0);
tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(1, i));
port->send_cs = ((tmp & 0x1) != 0);
port->send_we_n = ((tmp & 0x2) != 0);
port->send_run = ((tmp & 0x4) != 0);
port->send_ack = ((tmp & 0x8) != 0);
tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(2, i));
if (tmp & 0x1)
port->fifo_state = DMA_FIFO_STATE_WILL_BE_FULL;
if (tmp & 0x2)
port->fifo_state = DMA_FIFO_STATE_FULL;
if (tmp & 0x4)
port->fifo_state = DMA_FIFO_STATE_EMPTY;
port->fifo_counter = tmp >> 3;
}
for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
dma_channel_state_t *ch = &state->channel_states[i];
ch->connection = DMA_GET_CONNECTION(dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_PACKING_SETUP_PARAM)));
ch->sign_extend = DMA_GET_EXTENSION(dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_PACKING_SETUP_PARAM)));
ch->height = dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_HEIGHT_PARAM));
ch->stride_a = dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_STRIDE_A_PARAM));
ch->elems_a = DMA_GET_ELEMENTS(dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_ELEM_CROPPING_A_PARAM)));
ch->cropping_a = DMA_GET_CROPPING(dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_ELEM_CROPPING_A_PARAM)));
ch->width_a = dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_WIDTH_A_PARAM));
ch->stride_b = dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_STRIDE_B_PARAM));
ch->elems_b = DMA_GET_ELEMENTS(dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_ELEM_CROPPING_B_PARAM)));
ch->cropping_b = DMA_GET_CROPPING(dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_ELEM_CROPPING_B_PARAM)));
ch->width_b = dma_reg_load(ID,
DMA_CHANNEL_PARAM_REG_IDX(i,
_DMA_WIDTH_B_PARAM));
}
}
void
dma_set_max_burst_size(const dma_ID_t ID, dma_connection conn,
uint32_t max_burst_size)

116
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/dma_local.h
View File

@ -89,120 +89,4 @@
#define DMA_GET_ELEMENTS(val) _hrt_get_bits(val, _DMA_V2_ELEMENTS_IDX, _DMA_V2_ELEMENTS_BITS)
#define DMA_GET_CROPPING(val) _hrt_get_bits(val, _DMA_V2_LEFT_CROPPING_IDX, _DMA_V2_LEFT_CROPPING_BITS)
typedef enum {
DMA_CTRL_STATE_IDLE,
DMA_CTRL_STATE_REQ_RCV,
DMA_CTRL_STATE_RCV,
DMA_CTRL_STATE_RCV_REQ,
DMA_CTRL_STATE_INIT,
N_DMA_CTRL_STATES
} dma_ctrl_states_t;
typedef enum {
DMA_COMMAND_READ,
DMA_COMMAND_WRITE,
DMA_COMMAND_SET_CHANNEL,
DMA_COMMAND_SET_PARAM,
DMA_COMMAND_READ_SPECIFIC,
DMA_COMMAND_WRITE_SPECIFIC,
DMA_COMMAND_INIT,
DMA_COMMAND_INIT_SPECIFIC,
DMA_COMMAND_RST,
N_DMA_COMMANDS
} dma_commands_t;
typedef enum {
DMA_RW_STATE_IDLE,
DMA_RW_STATE_REQ,
DMA_RW_STATE_NEXT_LINE,
DMA_RW_STATE_UNLOCK_CHANNEL,
N_DMA_RW_STATES
} dma_rw_states_t;
typedef enum {
DMA_FIFO_STATE_WILL_BE_FULL,
DMA_FIFO_STATE_FULL,
DMA_FIFO_STATE_EMPTY,
N_DMA_FIFO_STATES
} dma_fifo_states_t;
/* typedef struct dma_state_s dma_state_t; */
typedef struct dma_channel_state_s dma_channel_state_t;
typedef struct dma_port_state_s dma_port_state_t;
struct dma_port_state_s {
bool req_cs;
bool req_we_n;
bool req_run;
bool req_ack;
bool send_cs;
bool send_we_n;
bool send_run;
bool send_ack;
dma_fifo_states_t fifo_state;
int fifo_counter;
};
struct dma_channel_state_s {
int connection;
bool sign_extend;
int height;
int stride_a;
int elems_a;
int cropping_a;
int width_a;
int stride_b;
int elems_b;
int cropping_b;
int width_b;
};
struct dma_state_s {
bool fsm_command_idle;
bool fsm_command_run;
bool fsm_command_stalling;
bool fsm_command_error;
dma_commands_t last_command;
int last_command_channel;
int last_command_param;
dma_commands_t current_command;
int current_addr_a;
int current_addr_b;
bool fsm_ctrl_idle;
bool fsm_ctrl_run;
bool fsm_ctrl_stalling;
bool fsm_ctrl_error;
dma_ctrl_states_t fsm_ctrl_state;
int fsm_ctrl_source_dev;
int fsm_ctrl_source_addr;
int fsm_ctrl_source_stride;
int fsm_ctrl_source_width;
int fsm_ctrl_source_height;
int fsm_ctrl_pack_source_dev;
int fsm_ctrl_pack_dest_dev;
int fsm_ctrl_dest_addr;
int fsm_ctrl_dest_stride;
int fsm_ctrl_pack_source_width;
int fsm_ctrl_pack_dest_height;
int fsm_ctrl_pack_dest_width;
int fsm_ctrl_pack_source_elems;
int fsm_ctrl_pack_dest_elems;
int fsm_ctrl_pack_extension;
int pack_idle;
int pack_run;
int pack_stalling;
int pack_error;
int pack_cnt_height;
int pack_src_cnt_width;
int pack_dest_cnt_width;
dma_rw_states_t read_state;
int read_cnt_height;
int read_cnt_width;
dma_rw_states_t write_state;
int write_height;
int write_width;
dma_port_state_t port_states[HIVE_ISP_NUM_DMA_CONNS];
dma_channel_state_t channel_states[HIVE_DMA_NUM_CHANNELS];
};
#endif /* __DMA_LOCAL_H_INCLUDED__ */

371
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/input_system.c
View File

@ -79,31 +79,6 @@ static input_system_err_t input_system_multiplexer_cfg(
const input_system_multiplex_t rhs,
input_system_config_flags_t *const flags);
static inline void capture_unit_get_state(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
capture_unit_state_t *state);
static inline void acquisition_unit_get_state(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
acquisition_unit_state_t *state);
static inline void ctrl_unit_get_state(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
ctrl_unit_state_t *state);
static inline void mipi_port_get_state(
const rx_ID_t ID,
const enum mipi_port_id port_ID,
mipi_port_state_t *state);
static inline void rx_channel_get_state(
const rx_ID_t ID,
const unsigned int ch_id,
rx_channel_state_t *state);
static void gp_device_rst(const gp_device_ID_t ID);
static void input_selector_cfg_for_sensor(const gp_device_ID_t ID);
@ -115,76 +90,6 @@ static void input_switch_cfg(
const input_switch_cfg_t *const cfg
);
void receiver_get_state(
const rx_ID_t ID,
receiver_state_t *state)
{
enum mipi_port_id port_id;
unsigned int ch_id;
assert(ID < N_RX_ID);
assert(state);
state->fs_to_ls_delay = (uint8_t)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX);
state->ls_to_data_delay = (uint8_t)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX);
state->data_to_le_delay = (uint8_t)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX);
state->le_to_fe_delay = (uint8_t)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX);
state->fe_to_fs_delay = (uint8_t)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX);
state->le_to_fs_delay = (uint8_t)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX);
state->is_two_ppc = (bool)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX);
state->backend_rst = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX);
state->raw18 = (uint16_t)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_RAW18_REG_IDX);
state->force_raw8 = (bool)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX);
state->raw16 = (uint16_t)receiver_reg_load(ID,
_HRT_CSS_RECEIVER_RAW16_REG_IDX);
for (port_id = (enum mipi_port_id)0; port_id < N_MIPI_PORT_ID; port_id++) {
mipi_port_get_state(ID, port_id,
&state->mipi_port_state[port_id]);
}
for (ch_id = 0U; ch_id < N_RX_CHANNEL_ID; ch_id++) {
rx_channel_get_state(ID, ch_id,
&state->rx_channel_state[ch_id]);
}
state->be_gsp_acc_ovl = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX);
state->be_srst = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_SRST_REG_IDX);
state->be_is_two_ppc = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX);
state->be_comp_format0 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX);
state->be_comp_format1 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX);
state->be_comp_format2 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX);
state->be_comp_format3 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX);
state->be_sel = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_SEL_REG_IDX);
state->be_raw16_config = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX);
state->be_raw18_config = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX);
state->be_force_raw8 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX);
state->be_irq_status = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX);
state->be_irq_clear = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX);
}
void receiver_set_compression(
const rx_ID_t ID,
const unsigned int cfg_ID,
@ -287,282 +192,6 @@ void receiver_irq_clear(
port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX, irq_info);
}
static inline void capture_unit_get_state(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
capture_unit_state_t *state)
{
assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= CAPTURE_UNIT2_ID));
assert(state);
state->StartMode = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_START_MODE_REG_ID);
state->Start_Addr = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_START_ADDR_REG_ID);
state->Mem_Region_Size = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_MEM_REGION_SIZE_REG_ID);
state->Num_Mem_Regions = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_NUM_MEM_REGIONS_REG_ID);
// AM: Illegal read from following registers.
/* state->Init = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_INIT_REG_ID);
state->Start = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_START_REG_ID);
state->Stop = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_STOP_REG_ID);
*/
state->Packet_Length = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_PACKET_LENGTH_REG_ID);
state->Received_Length = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_RECEIVED_LENGTH_REG_ID);
state->Received_Short_Packets = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_RECEIVED_SHORT_PACKETS_REG_ID);
state->Received_Long_Packets = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_RECEIVED_LONG_PACKETS_REG_ID);
state->Last_Command = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_LAST_COMMAND_REG_ID);
state->Next_Command = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_NEXT_COMMAND_REG_ID);
state->Last_Acknowledge = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_LAST_ACKNOWLEDGE_REG_ID);
state->Next_Acknowledge = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_NEXT_ACKNOWLEDGE_REG_ID);
state->FSM_State_Info = input_system_sub_system_reg_load(ID,
sub_id,
CAPT_FSM_STATE_INFO_REG_ID);
}
static inline void acquisition_unit_get_state(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
acquisition_unit_state_t *state)
{
assert(sub_id == ACQUISITION_UNIT0_ID);
assert(state);
state->Start_Addr = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_START_ADDR_REG_ID);
state->Mem_Region_Size = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_MEM_REGION_SIZE_REG_ID);
state->Num_Mem_Regions = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_NUM_MEM_REGIONS_REG_ID);
// AM: Illegal read from following registers.
/* state->Init = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_INIT_REG_ID);
*/
state->Received_Short_Packets = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_RECEIVED_SHORT_PACKETS_REG_ID);
state->Received_Long_Packets = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_RECEIVED_LONG_PACKETS_REG_ID);
state->Last_Command = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_LAST_COMMAND_REG_ID);
state->Next_Command = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_NEXT_COMMAND_REG_ID);
state->Last_Acknowledge = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_LAST_ACKNOWLEDGE_REG_ID);
state->Next_Acknowledge = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_NEXT_ACKNOWLEDGE_REG_ID);
state->FSM_State_Info = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_FSM_STATE_INFO_REG_ID);
state->Int_Cntr_Info = input_system_sub_system_reg_load(ID,
sub_id,
ACQ_INT_CNTR_INFO_REG_ID);
}
static inline void ctrl_unit_get_state(
const input_system_ID_t ID,
const sub_system_ID_t sub_id,
ctrl_unit_state_t *state)
{
assert(sub_id == CTRL_UNIT0_ID);
assert(state);
state->captA_start_addr = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_START_ADDR_A_REG_ID);
state->captB_start_addr = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_START_ADDR_B_REG_ID);
state->captC_start_addr = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_START_ADDR_C_REG_ID);
state->captA_mem_region_size = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID);
state->captB_mem_region_size = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID);
state->captC_mem_region_size = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID);
state->captA_num_mem_regions = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID);
state->captB_num_mem_regions = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID);
state->captC_num_mem_regions = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID);
state->acq_start_addr = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_ACQ_START_ADDR_REG_ID);
state->acq_mem_region_size = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID);
state->acq_num_mem_regions = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID);
// AM: Illegal read from following registers.
/* state->ctrl_init = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_INIT_REG_ID);
*/
state->last_cmd = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_LAST_COMMAND_REG_ID);
state->next_cmd = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_NEXT_COMMAND_REG_ID);
state->last_ack = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID);
state->next_ack = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID);
state->top_fsm_state = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_FSM_STATE_INFO_REG_ID);
state->captA_fsm_state = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID);
state->captB_fsm_state = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID);
state->captC_fsm_state = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID);
state->acq_fsm_state = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID);
state->capt_reserve_one_mem_region = input_system_sub_system_reg_load(ID,
sub_id,
ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID);
}
static inline void mipi_port_get_state(
const rx_ID_t ID,
const enum mipi_port_id port_ID,
mipi_port_state_t *state)
{
int i;
assert(ID < N_RX_ID);
assert(port_ID < N_MIPI_PORT_ID);
assert(state);
state->device_ready = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
state->irq_status = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
state->irq_enable = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
state->timeout_count = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX);
state->init_count = (uint16_t)receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX);
state->raw16_18 = (uint16_t)receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX);
state->sync_count = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX);
state->rx_count = receiver_port_reg_load(ID,
port_ID, _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX);
for (i = 0; i < MIPI_4LANE_CFG ; i++) {
state->lane_sync_count[i] = (uint8_t)((state->sync_count) >> (i * 8));
state->lane_rx_count[i] = (uint8_t)((state->rx_count) >> (i * 8));
}
}
static inline void rx_channel_get_state(
const rx_ID_t ID,
const unsigned int ch_id,
rx_channel_state_t *state)
{
int i;
assert(ID < N_RX_ID);
assert(ch_id < N_RX_CHANNEL_ID);
assert(state);
switch (ch_id) {
case 0:
state->comp_scheme0 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX);
state->comp_scheme1 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX);
break;
case 1:
state->comp_scheme0 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX);
state->comp_scheme1 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX);
break;
case 2:
state->comp_scheme0 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX);
state->comp_scheme1 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX);
break;
case 3:
state->comp_scheme0 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX);
state->comp_scheme1 = receiver_reg_load(ID,
_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX);
break;
}
/* See Table 7.1.17,..., 7.1.24 */
for (i = 0; i < 6; i++) {
u8 val = (uint8_t)((state->comp_scheme0) >> (i * 5)) & 0x1f;
state->comp[i] = (mipi_compressor_t)(val & 0x07);
state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3);
}
for (i = 6; i < N_MIPI_FORMAT_CUSTOM; i++) {
u8 val = (uint8_t)((state->comp_scheme0) >> ((i - 6) * 5)) & 0x1f;
state->comp[i] = (mipi_compressor_t)(val & 0x07);
state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3);
}
}
// MW: "2400" in the name is not good, but this is to avoid a naming conflict
static input_system_cfg2400_t config;

19
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq.c
View File

@ -225,25 +225,6 @@ void irq_raise(
return;
}
void irq_controller_get_state(const irq_ID_t ID,
struct irq_controller_state *state)
{
assert(ID < N_IRQ_ID);
assert(state);
state->irq_edge = irq_reg_load(ID,
_HRT_IRQ_CONTROLLER_EDGE_REG_IDX);
state->irq_mask = irq_reg_load(ID,
_HRT_IRQ_CONTROLLER_MASK_REG_IDX);
state->irq_status = irq_reg_load(ID,
_HRT_IRQ_CONTROLLER_STATUS_REG_IDX);
state->irq_enable = irq_reg_load(ID,
_HRT_IRQ_CONTROLLER_ENABLE_REG_IDX);
state->irq_level_not_pulse = irq_reg_load(ID,
_HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX);
return;
}
bool any_virq_signal(void)
{
unsigned int irq_status = irq_reg_load(IRQ0_ID,

8
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/irq_local.h
View File

@ -115,12 +115,4 @@ struct virq_info {
hrt_data irq_status_reg[N_IRQ_ID];
};
struct irq_controller_state {
unsigned int irq_edge;
unsigned int irq_mask;
unsigned int irq_status;
unsigned int irq_enable;
unsigned int irq_level_not_pulse;
};
#endif /* __IRQ_LOCAL_H_INCLUDED__ */

60
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp.c
View File

@ -39,66 +39,6 @@ void cnd_isp_irq_enable(
return;
}
void isp_get_state(
const isp_ID_t ID,
isp_state_t *state,
isp_stall_t *stall)
{
hrt_data sc = isp_ctrl_load(ID, ISP_SC_REG);
assert(state);
assert(stall);
#if defined(_hrt_sysmem_ident_address)
/* Patch to avoid compiler unused symbol warning in C_RUN build */
(void)__hrt_sysmem_ident_address;
(void)_hrt_sysmem_map_var;
#endif
state->pc = isp_ctrl_load(ID, ISP_PC_REG);
state->status_register = sc;
state->is_broken = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_BROKEN_BIT);
state->is_idle = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_IDLE_BIT);
state->is_sleeping = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_SLEEPING_BIT);
state->is_stalling = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_STALLING_BIT);
stall->stat_ctrl =
!isp_ctrl_getbit(ID, ISP_CTRL_SINK_REG, ISP_CTRL_SINK_BIT);
stall->pmem =
!isp_ctrl_getbit(ID, ISP_PMEM_SINK_REG, ISP_PMEM_SINK_BIT);
stall->dmem =
!isp_ctrl_getbit(ID, ISP_DMEM_SINK_REG, ISP_DMEM_SINK_BIT);
stall->vmem =
!isp_ctrl_getbit(ID, ISP_VMEM_SINK_REG, ISP_VMEM_SINK_BIT);
stall->fifo0 =
!isp_ctrl_getbit(ID, ISP_FIFO0_SINK_REG, ISP_FIFO0_SINK_BIT);
stall->fifo1 =
!isp_ctrl_getbit(ID, ISP_FIFO1_SINK_REG, ISP_FIFO1_SINK_BIT);
stall->fifo2 =
!isp_ctrl_getbit(ID, ISP_FIFO2_SINK_REG, ISP_FIFO2_SINK_BIT);
stall->fifo3 =
!isp_ctrl_getbit(ID, ISP_FIFO3_SINK_REG, ISP_FIFO3_SINK_BIT);
stall->fifo4 =
!isp_ctrl_getbit(ID, ISP_FIFO4_SINK_REG, ISP_FIFO4_SINK_BIT);
stall->fifo5 =
!isp_ctrl_getbit(ID, ISP_FIFO5_SINK_REG, ISP_FIFO5_SINK_BIT);
stall->fifo6 =
!isp_ctrl_getbit(ID, ISP_FIFO6_SINK_REG, ISP_FIFO6_SINK_BIT);
stall->vamem1 =
!isp_ctrl_getbit(ID, ISP_VAMEM1_SINK_REG, ISP_VAMEM1_SINK_BIT);
stall->vamem2 =
!isp_ctrl_getbit(ID, ISP_VAMEM2_SINK_REG, ISP_VAMEM2_SINK_BIT);
stall->vamem3 =
!isp_ctrl_getbit(ID, ISP_VAMEM3_SINK_REG, ISP_VAMEM3_SINK_BIT);
stall->hmem =
!isp_ctrl_getbit(ID, ISP_HMEM_SINK_REG, ISP_HMEM_SINK_BIT);
/*
stall->icache_master =
!isp_ctrl_getbit(ID, ISP_ICACHE_MT_SINK_REG,
ISP_ICACHE_MT_SINK_BIT);
*/
return;
}
/* ISP functions to control the ISP state from the host, even in crun. */
/* Inspect readiness of an ISP indexed by ID */

31
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/isp_local.h
View File

@ -22,35 +22,4 @@
#define HIVE_ISP_VMEM_MASK ((1U << ISP_VMEM_ELEMBITS) - 1)
typedef struct isp_state_s isp_state_t;
typedef struct isp_stall_s isp_stall_t;
struct isp_state_s {
int pc;
int status_register;
bool is_broken;
bool is_idle;
bool is_sleeping;
bool is_stalling;
};
struct isp_stall_s {
bool fifo0;
bool fifo1;
bool fifo2;
bool fifo3;
bool fifo4;
bool fifo5;
bool fifo6;
bool stat_ctrl;
bool dmem;
bool vmem;
bool vamem1;
bool vamem2;
bool vamem3;
bool hmem;
bool pmem;
bool icache_master;
};
#endif /* __ISP_LOCAL_H_INCLUDED__ */

47
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp.c
View File

@ -33,50 +33,3 @@ void cnd_sp_irq_enable(
sp_ctrl_clearbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT);
}
}
void sp_get_state(
const sp_ID_t ID,
sp_state_t *state,
sp_stall_t *stall)
{
hrt_data sc = sp_ctrl_load(ID, SP_SC_REG);
assert(state);
assert(stall);
state->pc = sp_ctrl_load(ID, SP_PC_REG);
state->status_register = sc;
state->is_broken = (sc & (1U << SP_BROKEN_BIT)) != 0;
state->is_idle = (sc & (1U << SP_IDLE_BIT)) != 0;
state->is_sleeping = (sc & (1U << SP_SLEEPING_BIT)) != 0;
state->is_stalling = (sc & (1U << SP_STALLING_BIT)) != 0;
stall->fifo0 =
!sp_ctrl_getbit(ID, SP_FIFO0_SINK_REG, SP_FIFO0_SINK_BIT);
stall->fifo1 =
!sp_ctrl_getbit(ID, SP_FIFO1_SINK_REG, SP_FIFO1_SINK_BIT);
stall->fifo2 =
!sp_ctrl_getbit(ID, SP_FIFO2_SINK_REG, SP_FIFO2_SINK_BIT);
stall->fifo3 =
!sp_ctrl_getbit(ID, SP_FIFO3_SINK_REG, SP_FIFO3_SINK_BIT);
stall->fifo4 =
!sp_ctrl_getbit(ID, SP_FIFO4_SINK_REG, SP_FIFO4_SINK_BIT);
stall->fifo5 =
!sp_ctrl_getbit(ID, SP_FIFO5_SINK_REG, SP_FIFO5_SINK_BIT);
stall->fifo6 =
!sp_ctrl_getbit(ID, SP_FIFO6_SINK_REG, SP_FIFO6_SINK_BIT);
stall->fifo7 =
!sp_ctrl_getbit(ID, SP_FIFO7_SINK_REG, SP_FIFO7_SINK_BIT);
stall->fifo8 =
!sp_ctrl_getbit(ID, SP_FIFO8_SINK_REG, SP_FIFO8_SINK_BIT);
stall->fifo9 =
!sp_ctrl_getbit(ID, SP_FIFO9_SINK_REG, SP_FIFO9_SINK_BIT);
stall->fifoa =
!sp_ctrl_getbit(ID, SP_FIFOA_SINK_REG, SP_FIFOA_SINK_BIT);
stall->dmem =
!sp_ctrl_getbit(ID, SP_DMEM_SINK_REG, SP_DMEM_SINK_BIT);
stall->control_master =
!sp_ctrl_getbit(ID, SP_CTRL_MT_SINK_REG, SP_CTRL_MT_SINK_BIT);
stall->icache_master =
!sp_ctrl_getbit(ID, SP_ICACHE_MT_SINK_REG,
SP_ICACHE_MT_SINK_BIT);
}

26
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/sp_local.h
View File

@ -19,32 +19,6 @@
#include <type_support.h>
#include "sp_global.h"
struct sp_state_s {
int pc;
int status_register;
bool is_broken;
bool is_idle;
bool is_sleeping;
bool is_stalling;
};
struct sp_stall_s {
bool fifo0;
bool fifo1;
bool fifo2;
bool fifo3;
bool fifo4;
bool fifo5;
bool fifo6;
bool fifo7;
bool fifo8;
bool fifo9;
bool fifoa;
bool dmem;
bool control_master;
bool icache_master;
};
#define sp_address_of(var) (HIVE_ADDR_ ## var)
/*

13
drivers/staging/media/atomisp/pci/hive_isp_css_include/host/dma_public.h
View File

@ -18,19 +18,6 @@
#include "system_local.h"
typedef struct dma_state_s dma_state_t;
/*! Read the control registers of DMA[ID]
\param ID[in] DMA identifier
\param state[out] input formatter state structure
\return none, state = DMA[ID].state
*/
void dma_get_state(
const dma_ID_t ID,
dma_state_t *state);
/*! Write to a control register of DMA[ID]
\param ID[in] DMA identifier

10
drivers/staging/media/atomisp/pci/hive_isp_css_include/host/irq_public.h
View File

@ -19,16 +19,6 @@
#include <type_support.h>
#include "system_local.h"
/*! Read the control registers of IRQ[ID]
\param ID[in] IRQ identifier
\param state[out] irq controller state structure
\return none, state = IRQ[ID].state
*/
void irq_controller_get_state(const irq_ID_t ID,
struct irq_controller_state *state);
/*! Write to a control register of IRQ[ID]
\param ID[in] IRQ identifier

13
drivers/staging/media/atomisp/pci/hive_isp_css_include/host/isp_public.h
View File

@ -30,19 +30,6 @@ void cnd_isp_irq_enable(
const isp_ID_t ID,
const bool cnd);
/*! Read the state of cell ISP[ID]
\param ID[in] ISP identifier
\param state[out] isp state structure
\param stall[out] isp stall conditions
\return none, state = ISP[ID].state, stall = ISP[ID].stall
*/
void isp_get_state(
const isp_ID_t ID,
isp_state_t *state,
isp_stall_t *stall);
/*! Write to the status and control register of ISP[ID]
\param ID[in] ISP identifier

16
drivers/staging/media/atomisp/pci/hive_isp_css_include/host/sp_public.h
View File

@ -19,9 +19,6 @@
#include <type_support.h>
#include "system_local.h"
typedef struct sp_state_s sp_state_t;
typedef struct sp_stall_s sp_stall_t;
/*! Enable or disable the program complete irq signal of SP[ID]
\param ID[in] SP identifier
@ -33,19 +30,6 @@ void cnd_sp_irq_enable(
const sp_ID_t ID,
const bool cnd);
/*! Read the state of cell SP[ID]
\param ID[in] SP identifier
\param state[out] sp state structure
\param stall[out] isp stall conditions
\return none, state = SP[ID].state, stall = SP[ID].stall
*/
void sp_get_state(
const sp_ID_t ID,
sp_state_t *state,
sp_stall_t *stall);
/*! Write to the status and control register of SP[ID]
\param ID[in] SP identifier

113
drivers/staging/media/atomisp/pci/isp2400_input_system_local.h
View File

@ -163,10 +163,6 @@ struct input_system_cfg2400_s {
#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX
#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS
typedef struct capture_unit_state_s capture_unit_state_t;
typedef struct acquisition_unit_state_s acquisition_unit_state_t;
typedef struct ctrl_unit_state_s ctrl_unit_state_t;
typedef enum {
MIPI_FORMAT_2400_RGB888 = 0,
MIPI_FORMAT_2400_RGB555,
@ -244,113 +240,4 @@ static const hrt_address __maybe_unused SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = {
0x0000C000UL
};
struct capture_unit_state_s {
int Packet_Length;
int Received_Length;
int Received_Short_Packets;
int Received_Long_Packets;
int Last_Command;
int Next_Command;
int Last_Acknowledge;
int Next_Acknowledge;
int FSM_State_Info;
int StartMode;
int Start_Addr;
int Mem_Region_Size;
int Num_Mem_Regions;
/* int Init; write-only registers
int Start;
int Stop; */
};
struct acquisition_unit_state_s {
/* int Init; write-only register */
int Received_Short_Packets;
int Received_Long_Packets;
int Last_Command;
int Next_Command;
int Last_Acknowledge;
int Next_Acknowledge;
int FSM_State_Info;
int Int_Cntr_Info;
int Start_Addr;
int Mem_Region_Size;
int Num_Mem_Regions;
};
struct ctrl_unit_state_s {
int last_cmd;
int next_cmd;
int last_ack;
int next_ack;
int top_fsm_state;
int captA_fsm_state;
int captB_fsm_state;
int captC_fsm_state;
int acq_fsm_state;
int captA_start_addr;
int captB_start_addr;
int captC_start_addr;
int captA_mem_region_size;
int captB_mem_region_size;
int captC_mem_region_size;
int captA_num_mem_regions;
int captB_num_mem_regions;
int captC_num_mem_regions;
int acq_start_addr;
int acq_mem_region_size;
int acq_num_mem_regions;
/* int ctrl_init; write only register */
int capt_reserve_one_mem_region;
};
struct mipi_port_state_s {
int device_ready;
int irq_status;
int irq_enable;
u32 timeout_count;
u16 init_count;
u16 raw16_18;
u32 sync_count; /*4 x uint8_t */
u32 rx_count; /*4 x uint8_t */
u8 lane_sync_count[MIPI_4LANE_CFG];
u8 lane_rx_count[MIPI_4LANE_CFG];
};
struct rx_channel_state_s {
u32 comp_scheme0;
u32 comp_scheme1;
mipi_predictor_t pred[N_MIPI_FORMAT_CUSTOM];
mipi_compressor_t comp[N_MIPI_FORMAT_CUSTOM];
};
struct receiver_state_s {
u8 fs_to_ls_delay;
u8 ls_to_data_delay;
u8 data_to_le_delay;
u8 le_to_fe_delay;
u8 fe_to_fs_delay;
u8 le_to_fs_delay;
bool is_two_ppc;
int backend_rst;
u16 raw18;
bool force_raw8;
u16 raw16;
struct mipi_port_state_s mipi_port_state[N_MIPI_PORT_ID];
struct rx_channel_state_s rx_channel_state[N_RX_CHANNEL_ID];
int be_gsp_acc_ovl;
int be_srst;
int be_is_two_ppc;
int be_comp_format0;
int be_comp_format1;
int be_comp_format2;
int be_comp_format3;
int be_sel;
int be_raw16_config;
int be_raw18_config;
int be_force_raw8;
int be_irq_status;
int be_irq_clear;
};
#endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */

28
drivers/staging/media/atomisp/pci/isp2400_input_system_public.h
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@ -18,34 +18,6 @@
#include <type_support.h>
typedef struct receiver_state_s receiver_state_t;
/*! Read the state of INPUT_SYSTEM[ID]
\param ID[in] INPUT_SYSTEM identifier
\param state[out] input system state structure
\return none, state = INPUT_SYSTEM[ID].state
*/
/*! Read the state of RECEIVER[ID]
\param ID[in] RECEIVER identifier
\param state[out] receiver state structure
\return none, state = RECEIVER[ID].state
*/
void receiver_get_state(
const rx_ID_t ID,
receiver_state_t *state);
/*! Flag whether a MIPI format is YUV420
\param mipi_format[in] MIPI format
\return mipi_format == YUV420
*/
/*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID]
\param ID[in] RECEIVER identifier

67
drivers/staging/media/atomisp/pci/runtime/debug/interface/ia_css_debug.h
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@ -154,18 +154,6 @@ void ia_css_debug_set_dtrace_level(
*/
unsigned int ia_css_debug_get_dtrace_level(void);
/*! @brief Dump isp hardware state.
* Dumps the isp hardware state to tracing output.
* @return None
*/
void ia_css_debug_dump_isp_state(void);
/*! @brief Dump sp hardware state.
* Dumps the sp hardware state to tracing output.
* @return None
*/
void ia_css_debug_dump_sp_state(void);
/* ISP2401 */
/*! @brief Dump GAC hardware state.
* Dumps the GAC ACB hardware registers. may be useful for
@ -174,25 +162,12 @@ void ia_css_debug_dump_sp_state(void);
*/
void ia_css_debug_dump_gac_state(void);
/*! @brief Dump dma controller state.
* Dumps the dma controller state to tracing output.
* @return None
*/
void ia_css_debug_dump_dma_state(void);
/*! @brief Dump internal sp software state.
* Dumps the sp software state to tracing output.
* @return None
*/
void ia_css_debug_dump_sp_sw_debug_info(void);
/*! @brief Dump all related hardware state to the trace output
* @param[in] context String to identify context in output.
* @return None
*/
void ia_css_debug_dump_debug_info(
const char *context);
#if SP_DEBUG != SP_DEBUG_NONE
void ia_css_debug_print_sp_debug_state(
const struct sh_css_sp_debug_state *state);
@ -207,24 +182,6 @@ void ia_css_debug_binary_print(
void ia_css_debug_sp_dump_mipi_fifo_high_water(void);
/*! @brief Dump isp gdc fifo state to the trace output
* Dumps the isp gdc fifo state to tracing output.
* @return None
*/
void ia_css_debug_dump_isp_gdc_fifo_state(void);
/*! @brief Dump dma isp fifo state
* Dumps the dma isp fifo state to tracing output.
* @return None
*/
void ia_css_debug_dump_dma_isp_fifo_state(void);
/*! @brief Dump dma sp fifo state
* Dumps the dma sp fifo state to tracing output.
* @return None
*/
void ia_css_debug_dump_dma_sp_fifo_state(void);
/*! \brief Dump pif A isp fifo state
* Dumps the primary input formatter state to tracing output.
* @return None
@ -243,24 +200,12 @@ void ia_css_debug_dump_pif_b_isp_fifo_state(void);
*/
void ia_css_debug_dump_str2mem_sp_fifo_state(void);
/*! @brief Dump isp sp fifo state
* Dumps the isp sp fifo state to tracing output.
* @return None
*/
void ia_css_debug_dump_isp_sp_fifo_state(void);
/*! @brief Dump all fifo state info to the output
* Dumps all fifo state to tracing output.
* @return None
*/
void ia_css_debug_dump_all_fifo_state(void);
/*! @brief Dump the rx state to the output
* Dumps the rx state to tracing output.
* @return None
*/
void ia_css_debug_dump_rx_state(void);
/*! @brief Dump the frame info to the trace output
* Dumps the frame info to tracing output.
* @param[in] frame pointer to struct ia_css_frame
@ -294,12 +239,6 @@ void ia_css_debug_wake_up_sp(void);
void ia_css_debug_dump_isp_params(struct ia_css_stream *stream,
unsigned int enable);
/*! @brief Function to dump some sp performance counters.
* Dump sp performance counters, currently input system errors.
* @return None
*/
void ia_css_debug_dump_perf_counters(void);
void ia_css_debug_dump_isp_binary(void);
void sh_css_dump_sp_raw_copy_linecount(bool reduced);
@ -382,12 +321,6 @@ void ia_css_debug_dump_stream_config(
const struct ia_css_stream_config *config,
int num_pipes);
/*! @brief Dump the state of the SP tagger
* Dumps the internal state of the SP tagger
* @return None
*/
void ia_css_debug_tagger_state(void);
/**
* @brief Initialize the debug mode.
*

1072
drivers/staging/media/atomisp/pci/runtime/debug/src/ia_css_debug.c
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