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MIPS: Add support for the 1074K core.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
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@ -94,6 +94,7 @@
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#define PRID_IMP_24KE 0x9600
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#define PRID_IMP_74K 0x9700
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#define PRID_IMP_1004K 0x9900
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#define PRID_IMP_1074K 0x9a00
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#define PRID_IMP_M14KC 0x9c00
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/*
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@ -596,6 +596,8 @@
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#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
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#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
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#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
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#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
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#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
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@ -857,6 +857,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
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c->cputype = CPU_1004K;
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__cpu_name[cpu] = "MIPS 1004Kc";
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break;
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case PRID_IMP_1074K:
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c->cputype = CPU_74K;
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__cpu_name[cpu] = "MIPS 1074Kc";
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break;
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}
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spram_config();
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@ -786,6 +786,25 @@ static inline void rm7k_erratum31(void)
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}
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}
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static inline void alias_74k_erratum(struct cpuinfo_mips *c)
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{
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/*
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* Early versions of the 74K do not update the cache tags on a
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* vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
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* aliases. In this case it is better to treat the cache as always
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* having aliases.
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*/
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if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
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c->dcache.flags |= MIPS_CACHE_VTAG;
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if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
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write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
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if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
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((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
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c->dcache.flags |= MIPS_CACHE_VTAG;
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write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
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}
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}
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static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
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"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
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};
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@ -1056,6 +1075,8 @@ static void __cpuinit probe_pcache(void)
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case CPU_34K:
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case CPU_74K:
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case CPU_1004K:
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if (c->cputype == CPU_74K)
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alias_74k_erratum(c);
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if ((read_c0_config7() & (1 << 16))) {
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/* effectively physically indexed dcache,
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thus no virtual aliases. */
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