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iommu/ipmmu-vmsa: Support clearing mappings
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Laurent Pinchart
Joerg Roedel
parent
bec0ca0333
commit
004c5b32fa
@ -192,14 +192,22 @@ static LIST_HEAD(ipmmu_devices);
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#define ARM_VMSA_PTE_SH_NS (((pteval_t)0) << 8)
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#define ARM_VMSA_PTE_SH_OS (((pteval_t)2) << 8)
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#define ARM_VMSA_PTE_SH_IS (((pteval_t)3) << 8)
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#define ARM_VMSA_PTE_SH_MASK (((pteval_t)3) << 8)
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#define ARM_VMSA_PTE_NS (((pteval_t)1) << 5)
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#define ARM_VMSA_PTE_PAGE (((pteval_t)3) << 0)
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/* Stage-1 PTE */
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#define ARM_VMSA_PTE_nG (((pteval_t)1) << 11)
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#define ARM_VMSA_PTE_AP_UNPRIV (((pteval_t)1) << 6)
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#define ARM_VMSA_PTE_AP_RDONLY (((pteval_t)2) << 6)
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#define ARM_VMSA_PTE_AP_MASK (((pteval_t)3) << 6)
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#define ARM_VMSA_PTE_ATTRINDX_MASK (((pteval_t)3) << 2)
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#define ARM_VMSA_PTE_ATTRINDX_SHIFT 2
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#define ARM_VMSA_PTE_nG (((pteval_t)1) << 11)
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#define ARM_VMSA_PTE_ATTRS_MASK \
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(ARM_VMSA_PTE_XN | ARM_VMSA_PTE_CONT | ARM_VMSA_PTE_nG | \
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ARM_VMSA_PTE_AF | ARM_VMSA_PTE_SH_MASK | ARM_VMSA_PTE_AP_MASK | \
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ARM_VMSA_PTE_NS | ARM_VMSA_PTE_ATTRINDX_MASK)
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#define ARM_VMSA_PTE_CONT_ENTRIES 16
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#define ARM_VMSA_PTE_CONT_SIZE (PAGE_SIZE * ARM_VMSA_PTE_CONT_ENTRIES)
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@ -614,7 +622,7 @@ static int ipmmu_alloc_init_pmd(struct ipmmu_vmsa_device *mmu, pmd_t *pmd,
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return 0;
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}
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static int ipmmu_handle_mapping(struct ipmmu_vmsa_domain *domain,
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static int ipmmu_create_mapping(struct ipmmu_vmsa_domain *domain,
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unsigned long iova, phys_addr_t paddr,
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size_t size, int prot)
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{
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@ -668,6 +676,180 @@ done:
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return ret;
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}
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static void ipmmu_clear_pud(struct ipmmu_vmsa_device *mmu, pud_t *pud)
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{
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/* Free the page table. */
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pgtable_t table = pud_pgtable(*pud);
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__free_page(table);
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/* Clear the PUD. */
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*pud = __pud(0);
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ipmmu_flush_pgtable(mmu, pud, sizeof(*pud));
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}
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static void ipmmu_clear_pmd(struct ipmmu_vmsa_device *mmu, pud_t *pud,
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pmd_t *pmd)
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{
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unsigned int i;
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/* Free the page table. */
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if (pmd_table(*pmd)) {
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pgtable_t table = pmd_pgtable(*pmd);
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__free_page(table);
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}
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/* Clear the PMD. */
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*pmd = __pmd(0);
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ipmmu_flush_pgtable(mmu, pmd, sizeof(*pmd));
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/* Check whether the PUD is still needed. */
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pmd = pmd_offset(pud, 0);
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for (i = 0; i < IPMMU_PTRS_PER_PMD; ++i) {
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if (!pmd_none(pmd[i]))
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return;
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}
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/* Clear the parent PUD. */
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ipmmu_clear_pud(mmu, pud);
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}
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static void ipmmu_clear_pte(struct ipmmu_vmsa_device *mmu, pud_t *pud,
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pmd_t *pmd, pte_t *pte, unsigned int num_ptes)
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{
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unsigned int i;
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/* Clear the PTE. */
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for (i = num_ptes; i; --i)
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pte[i-1] = __pte(0);
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ipmmu_flush_pgtable(mmu, pte, sizeof(*pte) * num_ptes);
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/* Check whether the PMD is still needed. */
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pte = pte_offset_kernel(pmd, 0);
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for (i = 0; i < IPMMU_PTRS_PER_PTE; ++i) {
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if (!pte_none(pte[i]))
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return;
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}
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/* Clear the parent PMD. */
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ipmmu_clear_pmd(mmu, pud, pmd);
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}
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static int ipmmu_split_pmd(struct ipmmu_vmsa_device *mmu, pmd_t *pmd)
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{
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pte_t *pte, *start;
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pteval_t pteval;
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unsigned long pfn;
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unsigned int i;
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pte = (pte_t *)get_zeroed_page(GFP_ATOMIC);
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if (!pte)
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return -ENOMEM;
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/* Copy the PMD attributes. */
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pteval = (pmd_val(*pmd) & ARM_VMSA_PTE_ATTRS_MASK)
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| ARM_VMSA_PTE_CONT | ARM_VMSA_PTE_PAGE;
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pfn = pmd_pfn(*pmd);
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start = pte;
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for (i = IPMMU_PTRS_PER_PTE; i; --i)
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*pte++ = pfn_pte(pfn++, __pgprot(pteval));
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ipmmu_flush_pgtable(mmu, start, PAGE_SIZE);
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*pmd = __pmd(__pa(start) | PMD_NSTABLE | PMD_TYPE_TABLE);
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ipmmu_flush_pgtable(mmu, pmd, sizeof(*pmd));
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return 0;
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}
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static void ipmmu_split_pte(struct ipmmu_vmsa_device *mmu, pte_t *pte)
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{
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unsigned int i;
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for (i = ARM_VMSA_PTE_CONT_ENTRIES; i; --i)
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pte[i-1] = __pte(pte_val(*pte) & ~ARM_VMSA_PTE_CONT);
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ipmmu_flush_pgtable(mmu, pte, sizeof(*pte) * ARM_VMSA_PTE_CONT_ENTRIES);
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}
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static int ipmmu_clear_mapping(struct ipmmu_vmsa_domain *domain,
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unsigned long iova, size_t size)
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{
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struct ipmmu_vmsa_device *mmu = domain->mmu;
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unsigned long flags;
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pgd_t *pgd = domain->pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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int ret = 0;
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if (!pgd)
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return -EINVAL;
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if (size & ~PAGE_MASK)
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return -EINVAL;
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pgd += pgd_index(iova);
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pud = (pud_t *)pgd;
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spin_lock_irqsave(&domain->lock, flags);
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/* If there's no PUD or PMD we're done. */
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if (pud_none(*pud))
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goto done;
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pmd = pmd_offset(pud, iova);
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if (pmd_none(*pmd))
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goto done;
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/*
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* When freeing a 2MB block just clear the PMD. In the unlikely case the
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* block is mapped as individual pages this will free the corresponding
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* PTE page table.
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*/
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if (size == SZ_2M) {
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ipmmu_clear_pmd(mmu, pud, pmd);
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goto done;
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}
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/*
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* If the PMD has been mapped as a section remap it as pages to allow
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* freeing individual pages.
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*/
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if (pmd_sect(*pmd))
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ipmmu_split_pmd(mmu, pmd);
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pte = pte_offset_kernel(pmd, iova);
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/*
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* When freeing a 64kB block just clear the PTE entries. We don't have
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* to care about the contiguous hint of the surrounding entries.
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*/
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if (size == SZ_64K) {
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ipmmu_clear_pte(mmu, pud, pmd, pte, ARM_VMSA_PTE_CONT_ENTRIES);
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goto done;
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}
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/*
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* If the PTE has been mapped with the contiguous hint set remap it and
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* its surrounding PTEs to allow unmapping a single page.
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*/
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if (pte_val(*pte) & ARM_VMSA_PTE_CONT)
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ipmmu_split_pte(mmu, pte);
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/* Clear the PTE. */
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ipmmu_clear_pte(mmu, pud, pmd, pte, 1);
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done:
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spin_unlock_irqrestore(&domain->lock, flags);
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if (ret)
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ipmmu_tlb_invalidate(domain);
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return 0;
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}
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/* -----------------------------------------------------------------------------
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* IOMMU Operations
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*/
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@ -768,7 +950,7 @@ static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
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if (!domain)
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return -ENODEV;
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return ipmmu_handle_mapping(domain, iova, paddr, size, prot);
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return ipmmu_create_mapping(domain, iova, paddr, size, prot);
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}
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static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
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@ -777,7 +959,7 @@ static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
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struct ipmmu_vmsa_domain *domain = io_domain->priv;
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int ret;
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ret = ipmmu_handle_mapping(domain, iova, 0, size, 0);
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ret = ipmmu_clear_mapping(domain, iova, size);
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return ret ? 0 : size;
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}
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