2005-04-16 22:20:36 +00:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
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*
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* Multi-arch abstraction and asm macros for easier reading:
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2011-04-04 21:15:29 +00:00
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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2005-04-16 22:20:36 +00:00
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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* Copyright (C) 1999, 2001 Silicon Graphics, Inc.
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*/
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#include <asm/asm.h>
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2015-06-22 11:20:59 +00:00
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#include <asm/asmmacro.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/errno.h>
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2017-06-05 18:21:28 +00:00
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#include <asm/export.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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2005-09-09 20:32:31 +00:00
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#include <asm/asm-offsets.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/regdef.h>
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2014-11-07 13:13:54 +00:00
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/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
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#undef fp
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2005-04-16 22:20:36 +00:00
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.macro EX insn, reg, src
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.set push
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2023-01-12 03:04:59 +00:00
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.set hardfloat
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2005-04-16 22:20:36 +00:00
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.set nomacro
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.ex\@: \insn \reg, \src
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.set pop
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.section __ex_table,"a"
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2022-01-25 14:19:44 +00:00
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PTR_WD .ex\@, fault
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2005-04-16 22:20:36 +00:00
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.previous
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.endm
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2017-06-05 18:21:28 +00:00
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/*
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* Save a thread's fp context.
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*/
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LEAF(_save_fp)
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EXPORT_SYMBOL(_save_fp)
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2017-07-03 22:41:47 +00:00
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 14:07:14 +00:00
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defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
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2017-06-05 18:21:28 +00:00
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mfc0 t0, CP0_STATUS
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#endif
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fpu_save_double a0 t0 t1 # clobbers t1
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jr ra
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END(_save_fp)
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/*
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* Restore a thread's fp context.
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*/
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LEAF(_restore_fp)
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2017-07-03 22:41:47 +00:00
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 14:07:14 +00:00
|
|
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defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
|
2017-06-05 18:21:28 +00:00
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|
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mfc0 t0, CP0_STATUS
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#endif
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fpu_restore_double a0 t0 t1 # clobbers t1
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jr ra
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END(_restore_fp)
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#ifdef CONFIG_CPU_HAS_MSA
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/*
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* Save a thread's MSA vector context.
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*/
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LEAF(_save_msa)
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EXPORT_SYMBOL(_save_msa)
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msa_save_all a0
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jr ra
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END(_save_msa)
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/*
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* Restore a thread's MSA vector context.
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*/
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LEAF(_restore_msa)
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msa_restore_all a0
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jr ra
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END(_restore_msa)
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LEAF(_init_msa_upper)
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msa_init_all_upper
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jr ra
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END(_init_msa_upper)
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#endif
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2005-04-16 22:20:36 +00:00
|
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.set noreorder
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2005-05-31 11:49:19 +00:00
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2015-07-27 19:58:15 +00:00
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/**
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* _save_fp_context() - save FP context from the FPU
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* @a0 - pointer to fpregs field of sigcontext
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|
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* @a1 - pointer to fpc_csr field of sigcontext
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|
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*
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* Save FP context, including the 32 FP data registers and the FP
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* control & status register, from the FPU to signal context.
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*/
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2005-04-16 22:20:36 +00:00
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LEAF(_save_fp_context)
|
2014-11-07 13:13:54 +00:00
|
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.set push
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2023-01-12 03:04:59 +00:00
|
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.set hardfloat
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2005-04-16 22:20:36 +00:00
|
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cfc1 t1, fcr31
|
2014-11-07 13:13:54 +00:00
|
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.set pop
|
2005-04-16 22:20:36 +00:00
|
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|
|
2017-07-03 22:41:47 +00:00
|
|
|
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
|
mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 14:07:14 +00:00
|
|
|
defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
|
2013-11-22 13:12:07 +00:00
|
|
|
.set push
|
2023-01-12 03:04:59 +00:00
|
|
|
.set hardfloat
|
mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 14:07:14 +00:00
|
|
|
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5)
|
2014-11-07 13:13:54 +00:00
|
|
|
.set mips32r2
|
|
|
|
|
.set fp=64
|
2013-11-22 13:12:07 +00:00
|
|
|
mfc0 t0, CP0_STATUS
|
|
|
|
|
sll t0, t0, 5
|
|
|
|
|
bgez t0, 1f # skip storing odd if FR=0
|
|
|
|
|
nop
|
|
|
|
|
#endif
|
2005-04-16 22:20:36 +00:00
|
|
|
/* Store the 16 odd double precision registers */
|
2015-07-27 19:58:15 +00:00
|
|
|
EX sdc1 $f1, 8(a0)
|
|
|
|
|
EX sdc1 $f3, 24(a0)
|
|
|
|
|
EX sdc1 $f5, 40(a0)
|
|
|
|
|
EX sdc1 $f7, 56(a0)
|
|
|
|
|
EX sdc1 $f9, 72(a0)
|
|
|
|
|
EX sdc1 $f11, 88(a0)
|
|
|
|
|
EX sdc1 $f13, 104(a0)
|
|
|
|
|
EX sdc1 $f15, 120(a0)
|
|
|
|
|
EX sdc1 $f17, 136(a0)
|
|
|
|
|
EX sdc1 $f19, 152(a0)
|
|
|
|
|
EX sdc1 $f21, 168(a0)
|
|
|
|
|
EX sdc1 $f23, 184(a0)
|
|
|
|
|
EX sdc1 $f25, 200(a0)
|
|
|
|
|
EX sdc1 $f27, 216(a0)
|
|
|
|
|
EX sdc1 $f29, 232(a0)
|
|
|
|
|
EX sdc1 $f31, 248(a0)
|
2013-11-22 13:12:07 +00:00
|
|
|
1: .set pop
|
2005-04-16 22:20:36 +00:00
|
|
|
#endif
|
|
|
|
|
|
2014-11-07 13:13:54 +00:00
|
|
|
.set push
|
2023-01-12 03:04:59 +00:00
|
|
|
.set hardfloat
|
2005-04-16 22:20:36 +00:00
|
|
|
/* Store the 16 even double precision registers */
|
2015-07-27 19:58:15 +00:00
|
|
|
EX sdc1 $f0, 0(a0)
|
|
|
|
|
EX sdc1 $f2, 16(a0)
|
|
|
|
|
EX sdc1 $f4, 32(a0)
|
|
|
|
|
EX sdc1 $f6, 48(a0)
|
|
|
|
|
EX sdc1 $f8, 64(a0)
|
|
|
|
|
EX sdc1 $f10, 80(a0)
|
|
|
|
|
EX sdc1 $f12, 96(a0)
|
|
|
|
|
EX sdc1 $f14, 112(a0)
|
|
|
|
|
EX sdc1 $f16, 128(a0)
|
|
|
|
|
EX sdc1 $f18, 144(a0)
|
|
|
|
|
EX sdc1 $f20, 160(a0)
|
|
|
|
|
EX sdc1 $f22, 176(a0)
|
|
|
|
|
EX sdc1 $f24, 192(a0)
|
|
|
|
|
EX sdc1 $f26, 208(a0)
|
|
|
|
|
EX sdc1 $f28, 224(a0)
|
|
|
|
|
EX sdc1 $f30, 240(a0)
|
|
|
|
|
EX sw t1, 0(a1)
|
2005-04-16 22:20:36 +00:00
|
|
|
jr ra
|
|
|
|
|
li v0, 0 # success
|
2014-11-07 13:13:54 +00:00
|
|
|
.set pop
|
2005-04-16 22:20:36 +00:00
|
|
|
END(_save_fp_context)
|
|
|
|
|
|
2015-07-27 19:58:15 +00:00
|
|
|
/**
|
|
|
|
|
* _restore_fp_context() - restore FP context to the FPU
|
|
|
|
|
* @a0 - pointer to fpregs field of sigcontext
|
|
|
|
|
* @a1 - pointer to fpc_csr field of sigcontext
|
|
|
|
|
*
|
|
|
|
|
* Restore FP context, including the 32 FP data registers and the FP
|
|
|
|
|
* control & status register, from signal context to the FPU.
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
|
|
|
|
LEAF(_restore_fp_context)
|
2015-07-27 19:58:15 +00:00
|
|
|
EX lw t1, 0(a1)
|
2013-11-22 13:12:07 +00:00
|
|
|
|
mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 14:07:14 +00:00
|
|
|
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
|
|
|
|
|
defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
|
2013-11-22 13:12:07 +00:00
|
|
|
.set push
|
2023-01-12 03:04:59 +00:00
|
|
|
.set hardfloat
|
mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 14:07:14 +00:00
|
|
|
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5)
|
2014-11-07 13:13:54 +00:00
|
|
|
.set mips32r2
|
|
|
|
|
.set fp=64
|
2013-11-22 13:12:07 +00:00
|
|
|
mfc0 t0, CP0_STATUS
|
|
|
|
|
sll t0, t0, 5
|
|
|
|
|
bgez t0, 1f # skip loading odd if FR=0
|
|
|
|
|
nop
|
|
|
|
|
#endif
|
2015-07-27 19:58:15 +00:00
|
|
|
EX ldc1 $f1, 8(a0)
|
|
|
|
|
EX ldc1 $f3, 24(a0)
|
|
|
|
|
EX ldc1 $f5, 40(a0)
|
|
|
|
|
EX ldc1 $f7, 56(a0)
|
|
|
|
|
EX ldc1 $f9, 72(a0)
|
|
|
|
|
EX ldc1 $f11, 88(a0)
|
|
|
|
|
EX ldc1 $f13, 104(a0)
|
|
|
|
|
EX ldc1 $f15, 120(a0)
|
|
|
|
|
EX ldc1 $f17, 136(a0)
|
|
|
|
|
EX ldc1 $f19, 152(a0)
|
|
|
|
|
EX ldc1 $f21, 168(a0)
|
|
|
|
|
EX ldc1 $f23, 184(a0)
|
|
|
|
|
EX ldc1 $f25, 200(a0)
|
|
|
|
|
EX ldc1 $f27, 216(a0)
|
|
|
|
|
EX ldc1 $f29, 232(a0)
|
|
|
|
|
EX ldc1 $f31, 248(a0)
|
2013-11-22 13:12:07 +00:00
|
|
|
1: .set pop
|
2005-04-16 22:20:36 +00:00
|
|
|
#endif
|
2014-11-07 13:13:54 +00:00
|
|
|
.set push
|
2023-01-12 03:04:59 +00:00
|
|
|
.set hardfloat
|
2015-07-27 19:58:15 +00:00
|
|
|
EX ldc1 $f0, 0(a0)
|
|
|
|
|
EX ldc1 $f2, 16(a0)
|
|
|
|
|
EX ldc1 $f4, 32(a0)
|
|
|
|
|
EX ldc1 $f6, 48(a0)
|
|
|
|
|
EX ldc1 $f8, 64(a0)
|
|
|
|
|
EX ldc1 $f10, 80(a0)
|
|
|
|
|
EX ldc1 $f12, 96(a0)
|
|
|
|
|
EX ldc1 $f14, 112(a0)
|
|
|
|
|
EX ldc1 $f16, 128(a0)
|
|
|
|
|
EX ldc1 $f18, 144(a0)
|
|
|
|
|
EX ldc1 $f20, 160(a0)
|
|
|
|
|
EX ldc1 $f22, 176(a0)
|
|
|
|
|
EX ldc1 $f24, 192(a0)
|
|
|
|
|
EX ldc1 $f26, 208(a0)
|
|
|
|
|
EX ldc1 $f28, 224(a0)
|
|
|
|
|
EX ldc1 $f30, 240(a0)
|
2014-02-07 14:31:33 +00:00
|
|
|
ctc1 t1, fcr31
|
2014-11-07 13:13:54 +00:00
|
|
|
.set pop
|
2005-04-16 22:20:36 +00:00
|
|
|
jr ra
|
|
|
|
|
li v0, 0 # success
|
|
|
|
|
END(_restore_fp_context)
|
|
|
|
|
|
2015-06-22 11:20:59 +00:00
|
|
|
#ifdef CONFIG_CPU_HAS_MSA
|
|
|
|
|
|
|
|
|
|
.macro op_one_wr op, idx, base
|
|
|
|
|
.align 4
|
|
|
|
|
\idx: \op \idx, 0, \base
|
|
|
|
|
jr ra
|
|
|
|
|
nop
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro op_msa_wr name, op
|
|
|
|
|
LEAF(\name)
|
|
|
|
|
.set push
|
|
|
|
|
.set noreorder
|
|
|
|
|
sll t0, a0, 4
|
|
|
|
|
PTR_LA t1, 0f
|
|
|
|
|
PTR_ADDU t0, t0, t1
|
|
|
|
|
jr t0
|
|
|
|
|
nop
|
|
|
|
|
op_one_wr \op, 0, a1
|
|
|
|
|
op_one_wr \op, 1, a1
|
|
|
|
|
op_one_wr \op, 2, a1
|
|
|
|
|
op_one_wr \op, 3, a1
|
|
|
|
|
op_one_wr \op, 4, a1
|
|
|
|
|
op_one_wr \op, 5, a1
|
|
|
|
|
op_one_wr \op, 6, a1
|
|
|
|
|
op_one_wr \op, 7, a1
|
|
|
|
|
op_one_wr \op, 8, a1
|
|
|
|
|
op_one_wr \op, 9, a1
|
|
|
|
|
op_one_wr \op, 10, a1
|
|
|
|
|
op_one_wr \op, 11, a1
|
|
|
|
|
op_one_wr \op, 12, a1
|
|
|
|
|
op_one_wr \op, 13, a1
|
|
|
|
|
op_one_wr \op, 14, a1
|
|
|
|
|
op_one_wr \op, 15, a1
|
|
|
|
|
op_one_wr \op, 16, a1
|
|
|
|
|
op_one_wr \op, 17, a1
|
|
|
|
|
op_one_wr \op, 18, a1
|
|
|
|
|
op_one_wr \op, 19, a1
|
|
|
|
|
op_one_wr \op, 20, a1
|
|
|
|
|
op_one_wr \op, 21, a1
|
|
|
|
|
op_one_wr \op, 22, a1
|
|
|
|
|
op_one_wr \op, 23, a1
|
|
|
|
|
op_one_wr \op, 24, a1
|
|
|
|
|
op_one_wr \op, 25, a1
|
|
|
|
|
op_one_wr \op, 26, a1
|
|
|
|
|
op_one_wr \op, 27, a1
|
|
|
|
|
op_one_wr \op, 28, a1
|
|
|
|
|
op_one_wr \op, 29, a1
|
|
|
|
|
op_one_wr \op, 30, a1
|
|
|
|
|
op_one_wr \op, 31, a1
|
|
|
|
|
.set pop
|
|
|
|
|
END(\name)
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
op_msa_wr read_msa_wr_b, st_b
|
|
|
|
|
op_msa_wr read_msa_wr_h, st_h
|
|
|
|
|
op_msa_wr read_msa_wr_w, st_w
|
|
|
|
|
op_msa_wr read_msa_wr_d, st_d
|
|
|
|
|
|
|
|
|
|
op_msa_wr write_msa_wr_b, ld_b
|
|
|
|
|
op_msa_wr write_msa_wr_h, ld_h
|
|
|
|
|
op_msa_wr write_msa_wr_w, ld_w
|
|
|
|
|
op_msa_wr write_msa_wr_d, ld_d
|
|
|
|
|
|
2015-07-27 19:58:22 +00:00
|
|
|
#endif /* CONFIG_CPU_HAS_MSA */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_CPU_HAS_MSA
|
|
|
|
|
|
|
|
|
|
.macro save_msa_upper wr, off, base
|
|
|
|
|
.set push
|
|
|
|
|
.set noat
|
|
|
|
|
#ifdef CONFIG_64BIT
|
2016-04-15 09:07:23 +00:00
|
|
|
copy_s_d \wr, 1
|
2015-07-27 19:58:22 +00:00
|
|
|
EX sd $1, \off(\base)
|
|
|
|
|
#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
|
2016-04-15 09:07:23 +00:00
|
|
|
copy_s_w \wr, 2
|
2015-07-27 19:58:22 +00:00
|
|
|
EX sw $1, \off(\base)
|
2016-04-15 09:07:23 +00:00
|
|
|
copy_s_w \wr, 3
|
2015-07-27 19:58:22 +00:00
|
|
|
EX sw $1, (\off+4)(\base)
|
|
|
|
|
#else /* CONFIG_CPU_BIG_ENDIAN */
|
2016-04-15 09:07:23 +00:00
|
|
|
copy_s_w \wr, 2
|
2015-07-27 19:58:22 +00:00
|
|
|
EX sw $1, (\off+4)(\base)
|
2016-04-15 09:07:23 +00:00
|
|
|
copy_s_w \wr, 3
|
2015-07-27 19:58:22 +00:00
|
|
|
EX sw $1, \off(\base)
|
|
|
|
|
#endif
|
|
|
|
|
.set pop
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
LEAF(_save_msa_all_upper)
|
|
|
|
|
save_msa_upper 0, 0x00, a0
|
|
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save_msa_upper 1, 0x08, a0
|
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save_msa_upper 2, 0x10, a0
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save_msa_upper 3, 0x18, a0
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save_msa_upper 4, 0x20, a0
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save_msa_upper 5, 0x28, a0
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save_msa_upper 6, 0x30, a0
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save_msa_upper 7, 0x38, a0
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save_msa_upper 8, 0x40, a0
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save_msa_upper 9, 0x48, a0
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save_msa_upper 10, 0x50, a0
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save_msa_upper 11, 0x58, a0
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save_msa_upper 12, 0x60, a0
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save_msa_upper 13, 0x68, a0
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save_msa_upper 14, 0x70, a0
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save_msa_upper 15, 0x78, a0
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save_msa_upper 16, 0x80, a0
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save_msa_upper 17, 0x88, a0
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save_msa_upper 18, 0x90, a0
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save_msa_upper 19, 0x98, a0
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save_msa_upper 20, 0xa0, a0
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save_msa_upper 21, 0xa8, a0
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|
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save_msa_upper 22, 0xb0, a0
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save_msa_upper 23, 0xb8, a0
|
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|
|
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save_msa_upper 24, 0xc0, a0
|
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|
|
|
save_msa_upper 25, 0xc8, a0
|
|
|
|
|
save_msa_upper 26, 0xd0, a0
|
|
|
|
|
save_msa_upper 27, 0xd8, a0
|
|
|
|
|
save_msa_upper 28, 0xe0, a0
|
|
|
|
|
save_msa_upper 29, 0xe8, a0
|
|
|
|
|
save_msa_upper 30, 0xf0, a0
|
|
|
|
|
save_msa_upper 31, 0xf8, a0
|
|
|
|
|
jr ra
|
|
|
|
|
li v0, 0
|
|
|
|
|
END(_save_msa_all_upper)
|
|
|
|
|
|
|
|
|
|
.macro restore_msa_upper wr, off, base
|
|
|
|
|
.set push
|
|
|
|
|
.set noat
|
|
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
|
EX ld $1, \off(\base)
|
|
|
|
|
insert_d \wr, 1
|
|
|
|
|
#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
|
|
|
|
|
EX lw $1, \off(\base)
|
|
|
|
|
insert_w \wr, 2
|
|
|
|
|
EX lw $1, (\off+4)(\base)
|
|
|
|
|
insert_w \wr, 3
|
|
|
|
|
#else /* CONFIG_CPU_BIG_ENDIAN */
|
|
|
|
|
EX lw $1, (\off+4)(\base)
|
|
|
|
|
insert_w \wr, 2
|
|
|
|
|
EX lw $1, \off(\base)
|
|
|
|
|
insert_w \wr, 3
|
|
|
|
|
#endif
|
|
|
|
|
.set pop
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
LEAF(_restore_msa_all_upper)
|
|
|
|
|
restore_msa_upper 0, 0x00, a0
|
|
|
|
|
restore_msa_upper 1, 0x08, a0
|
|
|
|
|
restore_msa_upper 2, 0x10, a0
|
|
|
|
|
restore_msa_upper 3, 0x18, a0
|
|
|
|
|
restore_msa_upper 4, 0x20, a0
|
|
|
|
|
restore_msa_upper 5, 0x28, a0
|
|
|
|
|
restore_msa_upper 6, 0x30, a0
|
|
|
|
|
restore_msa_upper 7, 0x38, a0
|
|
|
|
|
restore_msa_upper 8, 0x40, a0
|
|
|
|
|
restore_msa_upper 9, 0x48, a0
|
|
|
|
|
restore_msa_upper 10, 0x50, a0
|
|
|
|
|
restore_msa_upper 11, 0x58, a0
|
|
|
|
|
restore_msa_upper 12, 0x60, a0
|
|
|
|
|
restore_msa_upper 13, 0x68, a0
|
|
|
|
|
restore_msa_upper 14, 0x70, a0
|
|
|
|
|
restore_msa_upper 15, 0x78, a0
|
|
|
|
|
restore_msa_upper 16, 0x80, a0
|
|
|
|
|
restore_msa_upper 17, 0x88, a0
|
|
|
|
|
restore_msa_upper 18, 0x90, a0
|
|
|
|
|
restore_msa_upper 19, 0x98, a0
|
|
|
|
|
restore_msa_upper 20, 0xa0, a0
|
|
|
|
|
restore_msa_upper 21, 0xa8, a0
|
|
|
|
|
restore_msa_upper 22, 0xb0, a0
|
|
|
|
|
restore_msa_upper 23, 0xb8, a0
|
|
|
|
|
restore_msa_upper 24, 0xc0, a0
|
|
|
|
|
restore_msa_upper 25, 0xc8, a0
|
|
|
|
|
restore_msa_upper 26, 0xd0, a0
|
|
|
|
|
restore_msa_upper 27, 0xd8, a0
|
|
|
|
|
restore_msa_upper 28, 0xe0, a0
|
|
|
|
|
restore_msa_upper 29, 0xe8, a0
|
|
|
|
|
restore_msa_upper 30, 0xf0, a0
|
|
|
|
|
restore_msa_upper 31, 0xf8, a0
|
|
|
|
|
jr ra
|
|
|
|
|
li v0, 0
|
|
|
|
|
END(_restore_msa_all_upper)
|
|
|
|
|
|
2015-06-22 11:20:59 +00:00
|
|
|
#endif /* CONFIG_CPU_HAS_MSA */
|
|
|
|
|
|
2007-02-01 19:54:13 +00:00
|
|
|
.set reorder
|
|
|
|
|
|
2016-02-23 10:29:20 +00:00
|
|
|
.type fault, @function
|
2005-04-16 22:20:36 +00:00
|
|
|
.ent fault
|
|
|
|
|
fault: li v0, -EFAULT # failure
|
|
|
|
|
jr ra
|
|
|
|
|
.end fault
|
