License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0
|
2008-02-23 01:28:37 +00:00
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/clocksource.h>
|
|
|
|
#include <linux/clockchips.h>
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/irq.h>
|
|
|
|
|
|
|
|
#include <linux/clk.h>
|
|
|
|
#include <linux/err.h>
|
|
|
|
#include <linux/ioport.h>
|
|
|
|
#include <linux/io.h>
|
2019-04-26 21:47:11 +00:00
|
|
|
#include <linux/of_address.h>
|
|
|
|
#include <linux/of_irq.h>
|
2019-04-26 21:47:12 +00:00
|
|
|
#include <linux/sched_clock.h>
|
2017-05-12 18:22:51 +00:00
|
|
|
#include <linux/syscore_ops.h>
|
2019-04-26 21:47:10 +00:00
|
|
|
#include <soc/at91/atmel_tcb.h>
|
2008-02-23 01:28:37 +00:00
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We're configured to use a specific TC block, one that's not hooked
|
|
|
|
* up to external hardware, to provide a time solution:
|
|
|
|
*
|
|
|
|
* - Two channels combine to create a free-running 32 bit counter
|
|
|
|
* with a base rate of 5+ MHz, packaged as a clocksource (with
|
|
|
|
* resolution better than 200 nsec).
|
2012-01-19 17:44:49 +00:00
|
|
|
* - Some chips support 32 bit counter. A single channel is used for
|
|
|
|
* this 32 bit free-running counter. the second channel is not used.
|
2008-02-23 01:28:37 +00:00
|
|
|
*
|
|
|
|
* - The third channel may be used to provide a 16-bit clockevent
|
|
|
|
* source, used in either periodic or oneshot mode. This runs
|
|
|
|
* at 32 KiHZ, and can handle delays of up to two seconds.
|
|
|
|
*
|
|
|
|
* REVISIT behavior during system suspend states... we should disable
|
|
|
|
* all clocks and save the power. Easily done for clockevent devices,
|
|
|
|
* but clocksources won't necessarily get the needed notifications.
|
|
|
|
* For deeper system sleep states, this will be mandatory...
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void __iomem *tcaddr;
|
2017-05-12 18:22:51 +00:00
|
|
|
static struct
|
|
|
|
{
|
|
|
|
u32 cmr;
|
|
|
|
u32 imr;
|
|
|
|
u32 rc;
|
|
|
|
bool clken;
|
|
|
|
} tcb_cache[3];
|
|
|
|
static u32 bmr_cache;
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2016-12-21 19:32:01 +00:00
|
|
|
static u64 tc_get_cycles(struct clocksource *cs)
|
2008-02-23 01:28:37 +00:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
u32 lower, upper;
|
|
|
|
|
|
|
|
raw_local_irq_save(flags);
|
|
|
|
do {
|
2017-06-23 15:03:31 +00:00
|
|
|
upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
|
|
|
|
lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
|
|
|
|
} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));
|
2008-02-23 01:28:37 +00:00
|
|
|
|
|
|
|
raw_local_irq_restore(flags);
|
|
|
|
return (upper << 16) | lower;
|
|
|
|
}
|
|
|
|
|
2017-01-11 13:50:59 +00:00
|
|
|
static u64 tc_get_cycles32(struct clocksource *cs)
|
|
|
|
{
|
2017-06-23 15:03:31 +00:00
|
|
|
return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
|
2017-01-11 13:50:59 +00:00
|
|
|
}
|
|
|
|
|
2019-04-26 21:47:17 +00:00
|
|
|
static void tc_clksrc_suspend(struct clocksource *cs)
|
2017-05-12 18:22:51 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
|
|
|
|
tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
|
|
|
|
tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
|
|
|
|
tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
|
|
|
|
tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
|
|
|
|
ATMEL_TC_CLKSTA);
|
|
|
|
}
|
|
|
|
|
|
|
|
bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
|
|
|
|
}
|
|
|
|
|
2019-04-26 21:47:17 +00:00
|
|
|
static void tc_clksrc_resume(struct clocksource *cs)
|
2017-05-12 18:22:51 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
|
|
|
|
/* Restore registers for the channel, RA and RB are not used */
|
|
|
|
writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
|
|
|
|
writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
|
|
|
|
writel(0, tcaddr + ATMEL_TC_REG(i, RA));
|
|
|
|
writel(0, tcaddr + ATMEL_TC_REG(i, RB));
|
|
|
|
/* Disable all the interrupts */
|
|
|
|
writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
|
|
|
|
/* Reenable interrupts that were enabled before suspending */
|
|
|
|
writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
|
|
|
|
/* Start the clock if it was used */
|
|
|
|
if (tcb_cache[i].clken)
|
|
|
|
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Dual channel, chain channels */
|
|
|
|
writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
|
|
|
|
/* Finally, trigger all the channels*/
|
|
|
|
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
|
|
|
|
}
|
|
|
|
|
2008-02-23 01:28:37 +00:00
|
|
|
static struct clocksource clksrc = {
|
|
|
|
.rating = 200,
|
|
|
|
.read = tc_get_cycles,
|
|
|
|
.mask = CLOCKSOURCE_MASK(32),
|
|
|
|
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
2017-05-12 18:22:51 +00:00
|
|
|
.suspend = tc_clksrc_suspend,
|
|
|
|
.resume = tc_clksrc_resume,
|
2008-02-23 01:28:37 +00:00
|
|
|
};
|
|
|
|
|
2019-04-26 21:47:12 +00:00
|
|
|
static u64 notrace tc_sched_clock_read(void)
|
|
|
|
{
|
|
|
|
return tc_get_cycles(&clksrc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u64 notrace tc_sched_clock_read32(void)
|
|
|
|
{
|
|
|
|
return tc_get_cycles32(&clksrc);
|
|
|
|
}
|
|
|
|
|
2008-02-23 01:28:37 +00:00
|
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS
|
|
|
|
|
|
|
|
struct tc_clkevt_device {
|
|
|
|
struct clock_event_device clkevt;
|
|
|
|
struct clk *clk;
|
|
|
|
void __iomem *regs;
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
|
|
|
|
{
|
|
|
|
return container_of(clkevt, struct tc_clkevt_device, clkevt);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
|
|
|
|
* because using one of the divided clocks would usually mean the
|
|
|
|
* tick rate can never be less than several dozen Hz (vs 0.5 Hz).
|
|
|
|
*
|
|
|
|
* A divided clock could be good for high resolution timers, since
|
|
|
|
* 30.5 usec resolution can seem "low".
|
|
|
|
*/
|
|
|
|
static u32 timer_clock;
|
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
static int tc_shutdown(struct clock_event_device *d)
|
2008-02-23 01:28:37 +00:00
|
|
|
{
|
|
|
|
struct tc_clkevt_device *tcd = to_tc_clkevt(d);
|
|
|
|
void __iomem *regs = tcd->regs;
|
|
|
|
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(0xff, regs + ATMEL_TC_REG(2, IDR));
|
|
|
|
writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
|
2016-01-15 10:34:21 +00:00
|
|
|
if (!clockevent_state_detached(d))
|
|
|
|
clk_disable(tcd->clk);
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
static int tc_set_oneshot(struct clock_event_device *d)
|
|
|
|
{
|
|
|
|
struct tc_clkevt_device *tcd = to_tc_clkevt(d);
|
|
|
|
void __iomem *regs = tcd->regs;
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
|
|
|
|
tc_shutdown(d);
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
clk_enable(tcd->clk);
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
/* slow clock, count up to RC, then irq and stop */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
|
2015-06-18 10:54:38 +00:00
|
|
|
ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
/* set_next_event() configures and starts the timer */
|
|
|
|
return 0;
|
|
|
|
}
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
static int tc_set_periodic(struct clock_event_device *d)
|
|
|
|
{
|
|
|
|
struct tc_clkevt_device *tcd = to_tc_clkevt(d);
|
|
|
|
void __iomem *regs = tcd->regs;
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
|
|
|
|
tc_shutdown(d);
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2015-06-18 10:54:38 +00:00
|
|
|
/* By not making the gentime core emulate periodic mode on top
|
|
|
|
* of oneshot, we get lower overhead and improved accuracy.
|
|
|
|
*/
|
|
|
|
clk_enable(tcd->clk);
|
|
|
|
|
|
|
|
/* slow clock, count up to RC, then irq and restart */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
|
2015-06-18 10:54:38 +00:00
|
|
|
regs + ATMEL_TC_REG(2, CMR));
|
2017-06-23 15:03:31 +00:00
|
|
|
writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
|
2015-06-18 10:54:38 +00:00
|
|
|
|
|
|
|
/* Enable clock and interrupts on RC compare */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
|
2015-06-18 10:54:38 +00:00
|
|
|
|
|
|
|
/* go go gadget! */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
|
2015-06-18 10:54:38 +00:00
|
|
|
ATMEL_TC_REG(2, CCR));
|
|
|
|
return 0;
|
2008-02-23 01:28:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int tc_next_event(unsigned long delta, struct clock_event_device *d)
|
|
|
|
{
|
2017-06-23 15:03:31 +00:00
|
|
|
writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));
|
2008-02-23 01:28:37 +00:00
|
|
|
|
|
|
|
/* go go gadget! */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
|
2008-02-23 01:28:37 +00:00
|
|
|
tcaddr + ATMEL_TC_REG(2, CCR));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct tc_clkevt_device clkevt = {
|
|
|
|
.clkevt = {
|
2015-06-18 10:54:38 +00:00
|
|
|
.features = CLOCK_EVT_FEAT_PERIODIC |
|
|
|
|
CLOCK_EVT_FEAT_ONESHOT,
|
2008-02-23 01:28:37 +00:00
|
|
|
/* Should be lower than at91rm9200's system timer */
|
2015-06-18 10:54:38 +00:00
|
|
|
.rating = 125,
|
|
|
|
.set_next_event = tc_next_event,
|
|
|
|
.set_state_shutdown = tc_shutdown,
|
|
|
|
.set_state_periodic = tc_set_periodic,
|
|
|
|
.set_state_oneshot = tc_set_oneshot,
|
2008-02-23 01:28:37 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static irqreturn_t ch2_irq(int irq, void *handle)
|
|
|
|
{
|
|
|
|
struct tc_clkevt_device *dev = handle;
|
|
|
|
unsigned int sr;
|
|
|
|
|
2017-06-23 15:03:31 +00:00
|
|
|
sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
|
2008-02-23 01:28:37 +00:00
|
|
|
if (sr & ATMEL_TC_CPCS) {
|
|
|
|
dev->clkevt.event_handler(&dev->clkevt);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
2013-10-02 12:35:41 +00:00
|
|
|
static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
|
2008-02-23 01:28:37 +00:00
|
|
|
{
|
2013-10-02 12:35:41 +00:00
|
|
|
int ret;
|
2008-02-23 01:28:37 +00:00
|
|
|
struct clk *t2_clk = tc->clk[2];
|
|
|
|
int irq = tc->irq[2];
|
|
|
|
|
2015-08-16 09:23:46 +00:00
|
|
|
ret = clk_prepare_enable(tc->slow_clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2013-10-02 12:35:41 +00:00
|
|
|
/* try to enable t2 clk to avoid future errors in mode change */
|
|
|
|
ret = clk_prepare_enable(t2_clk);
|
2015-08-16 09:23:46 +00:00
|
|
|
if (ret) {
|
|
|
|
clk_disable_unprepare(tc->slow_clk);
|
2013-10-02 12:35:41 +00:00
|
|
|
return ret;
|
2015-08-16 09:23:46 +00:00
|
|
|
}
|
|
|
|
|
2014-05-08 10:06:25 +00:00
|
|
|
clk_disable(t2_clk);
|
2013-10-02 12:35:41 +00:00
|
|
|
|
2008-02-23 01:28:37 +00:00
|
|
|
clkevt.regs = tc->regs;
|
|
|
|
clkevt.clk = t2_clk;
|
|
|
|
|
|
|
|
timer_clock = clk32k_divisor_idx;
|
|
|
|
|
2008-12-13 10:50:26 +00:00
|
|
|
clkevt.clkevt.cpumask = cpumask_of(0);
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2014-09-06 17:52:37 +00:00
|
|
|
ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
|
|
|
|
if (ret) {
|
2015-08-16 09:23:45 +00:00
|
|
|
clk_unprepare(t2_clk);
|
2015-08-16 09:23:46 +00:00
|
|
|
clk_disable_unprepare(tc->slow_clk);
|
2013-10-02 12:35:41 +00:00
|
|
|
return ret;
|
2014-09-06 17:52:37 +00:00
|
|
|
}
|
2013-10-02 12:35:41 +00:00
|
|
|
|
2013-01-12 11:50:06 +00:00
|
|
|
clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
|
2011-01-25 23:07:29 +00:00
|
|
|
|
2013-10-02 12:35:41 +00:00
|
|
|
return ret;
|
2008-02-23 01:28:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#else /* !CONFIG_GENERIC_CLOCKEVENTS */
|
|
|
|
|
2013-10-02 12:35:41 +00:00
|
|
|
static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
|
2008-02-23 01:28:37 +00:00
|
|
|
{
|
|
|
|
/* NOTHING */
|
2013-10-02 12:35:41 +00:00
|
|
|
return 0;
|
2008-02-23 01:28:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2012-01-19 17:44:49 +00:00
|
|
|
static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
|
|
|
|
{
|
|
|
|
/* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(mck_divisor_idx /* likely divide-by-8 */
|
2012-01-19 17:44:49 +00:00
|
|
|
| ATMEL_TC_WAVE
|
|
|
|
| ATMEL_TC_WAVESEL_UP /* free-run */
|
|
|
|
| ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
|
|
|
|
| ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
|
|
|
|
tcaddr + ATMEL_TC_REG(0, CMR));
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
|
|
|
|
writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
|
|
|
|
writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
|
|
|
|
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
|
2012-01-19 17:44:49 +00:00
|
|
|
|
|
|
|
/* channel 1: waveform mode, input TIOA0 */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(ATMEL_TC_XC1 /* input: TIOA0 */
|
2012-01-19 17:44:49 +00:00
|
|
|
| ATMEL_TC_WAVE
|
|
|
|
| ATMEL_TC_WAVESEL_UP, /* free-run */
|
|
|
|
tcaddr + ATMEL_TC_REG(1, CMR));
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
|
|
|
|
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
|
2012-01-19 17:44:49 +00:00
|
|
|
|
|
|
|
/* chain channel 0 to channel 1*/
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
|
2012-01-19 17:44:49 +00:00
|
|
|
/* then reset all the timers */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
|
2012-01-19 17:44:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
|
|
|
|
{
|
|
|
|
/* channel 0: waveform mode, input mclk/8 */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(mck_divisor_idx /* likely divide-by-8 */
|
2012-01-19 17:44:49 +00:00
|
|
|
| ATMEL_TC_WAVE
|
|
|
|
| ATMEL_TC_WAVESEL_UP, /* free-run */
|
|
|
|
tcaddr + ATMEL_TC_REG(0, CMR));
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
|
|
|
|
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
|
2012-01-19 17:44:49 +00:00
|
|
|
|
|
|
|
/* then reset all the timers */
|
2017-06-23 15:03:31 +00:00
|
|
|
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
|
2012-01-19 17:44:49 +00:00
|
|
|
}
|
|
|
|
|
2019-04-26 21:47:11 +00:00
|
|
|
static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, };
|
|
|
|
|
|
|
|
static const struct of_device_id atmel_tcb_of_match[] = {
|
|
|
|
{ .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
|
|
|
|
{ .compatible = "atmel,at91sam9x5-tcb", .data = (void *)32, },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2019-04-26 21:47:11 +00:00
|
|
|
static int __init tcb_clksrc_init(struct device_node *node)
|
|
|
|
{
|
|
|
|
struct atmel_tc tc;
|
2008-03-13 17:44:48 +00:00
|
|
|
struct clk *t0_clk;
|
2019-04-26 21:47:11 +00:00
|
|
|
const struct of_device_id *match;
|
2019-04-26 21:47:12 +00:00
|
|
|
u64 (*tc_sched_clock)(void);
|
2008-02-23 01:28:37 +00:00
|
|
|
u32 rate, divided_rate = 0;
|
|
|
|
int best_divisor_idx = -1;
|
|
|
|
int clk32k_divisor_idx = -1;
|
2019-04-26 21:47:11 +00:00
|
|
|
int bits;
|
2008-02-23 01:28:37 +00:00
|
|
|
int i;
|
2013-10-02 12:35:20 +00:00
|
|
|
int ret;
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2019-04-26 21:47:11 +00:00
|
|
|
/* Protect against multiple calls */
|
|
|
|
if (tcaddr)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
tc.regs = of_iomap(node->parent, 0);
|
|
|
|
if (!tc.regs)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
t0_clk = of_clk_get_by_name(node->parent, "t0_clk");
|
|
|
|
if (IS_ERR(t0_clk))
|
|
|
|
return PTR_ERR(t0_clk);
|
|
|
|
|
|
|
|
tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
|
|
|
|
if (IS_ERR(tc.slow_clk))
|
|
|
|
return PTR_ERR(tc.slow_clk);
|
|
|
|
|
|
|
|
tc.clk[0] = t0_clk;
|
|
|
|
tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk");
|
|
|
|
if (IS_ERR(tc.clk[1]))
|
|
|
|
tc.clk[1] = t0_clk;
|
|
|
|
tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk");
|
|
|
|
if (IS_ERR(tc.clk[2]))
|
|
|
|
tc.clk[2] = t0_clk;
|
|
|
|
|
|
|
|
tc.irq[2] = of_irq_get(node->parent, 2);
|
|
|
|
if (tc.irq[2] <= 0) {
|
|
|
|
tc.irq[2] = of_irq_get(node->parent, 0);
|
|
|
|
if (tc.irq[2] <= 0)
|
|
|
|
return -EINVAL;
|
2008-02-23 01:28:37 +00:00
|
|
|
}
|
|
|
|
|
2019-04-26 21:47:11 +00:00
|
|
|
match = of_match_node(atmel_tcb_of_match, node->parent);
|
|
|
|
bits = (uintptr_t)match->data;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(tc.irq); i++)
|
|
|
|
writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));
|
|
|
|
|
2013-10-02 12:35:20 +00:00
|
|
|
ret = clk_prepare_enable(t0_clk);
|
|
|
|
if (ret) {
|
|
|
|
pr_debug("can't enable T0 clk\n");
|
2019-04-26 21:47:11 +00:00
|
|
|
return ret;
|
2013-10-02 12:35:20 +00:00
|
|
|
}
|
2008-02-23 01:28:37 +00:00
|
|
|
|
|
|
|
/* How fast will we be counting? Pick something over 5 MHz. */
|
|
|
|
rate = (u32) clk_get_rate(t0_clk);
|
2019-04-26 21:47:11 +00:00
|
|
|
for (i = 0; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
|
|
|
|
unsigned divisor = atmel_tcb_divisors[i];
|
2008-02-23 01:28:37 +00:00
|
|
|
unsigned tmp;
|
|
|
|
|
|
|
|
/* remember 32 KiHz clock for later */
|
|
|
|
if (!divisor) {
|
|
|
|
clk32k_divisor_idx = i;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp = rate / divisor;
|
|
|
|
pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
|
|
|
|
if (best_divisor_idx > 0) {
|
|
|
|
if (tmp < 5 * 1000 * 1000)
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
divided_rate = tmp;
|
|
|
|
best_divisor_idx = i;
|
|
|
|
}
|
|
|
|
|
2019-04-26 21:47:11 +00:00
|
|
|
clksrc.name = kbasename(node->parent->full_name);
|
|
|
|
clkevt.clkevt.name = kbasename(node->parent->full_name);
|
|
|
|
pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000,
|
2018-01-08 13:28:43 +00:00
|
|
|
((divided_rate % 1000000) + 500) / 1000);
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2019-04-26 21:47:11 +00:00
|
|
|
tcaddr = tc.regs;
|
|
|
|
|
|
|
|
if (bits == 32) {
|
2012-01-19 17:44:49 +00:00
|
|
|
/* use apropriate function to read 32 bit counter */
|
|
|
|
clksrc.read = tc_get_cycles32;
|
|
|
|
/* setup ony channel 0 */
|
2019-04-26 21:47:11 +00:00
|
|
|
tcb_setup_single_chan(&tc, best_divisor_idx);
|
2019-04-26 21:47:12 +00:00
|
|
|
tc_sched_clock = tc_sched_clock_read32;
|
2012-01-19 17:44:49 +00:00
|
|
|
} else {
|
2019-04-26 21:47:11 +00:00
|
|
|
/* we have three clocks no matter what the
|
2012-01-19 17:44:49 +00:00
|
|
|
* underlying platform supports.
|
|
|
|
*/
|
2019-04-26 21:47:11 +00:00
|
|
|
ret = clk_prepare_enable(tc.clk[1]);
|
2013-10-02 12:35:20 +00:00
|
|
|
if (ret) {
|
|
|
|
pr_debug("can't enable T1 clk\n");
|
|
|
|
goto err_disable_t0;
|
|
|
|
}
|
2012-01-19 17:44:49 +00:00
|
|
|
/* setup both channel 0 & 1 */
|
2019-04-26 21:47:11 +00:00
|
|
|
tcb_setup_dual_chan(&tc, best_divisor_idx);
|
2019-04-26 21:47:12 +00:00
|
|
|
tc_sched_clock = tc_sched_clock_read;
|
2012-01-19 17:44:49 +00:00
|
|
|
}
|
2008-02-23 01:28:37 +00:00
|
|
|
|
|
|
|
/* and away we go! */
|
2013-10-02 12:35:41 +00:00
|
|
|
ret = clocksource_register_hz(&clksrc, divided_rate);
|
|
|
|
if (ret)
|
|
|
|
goto err_disable_t1;
|
2008-02-23 01:28:37 +00:00
|
|
|
|
|
|
|
/* channel 2: periodic and oneshot timer support */
|
2019-04-26 21:47:11 +00:00
|
|
|
ret = setup_clkevents(&tc, clk32k_divisor_idx);
|
2013-10-02 12:35:41 +00:00
|
|
|
if (ret)
|
|
|
|
goto err_unregister_clksrc;
|
2008-02-23 01:28:37 +00:00
|
|
|
|
2019-04-26 21:47:12 +00:00
|
|
|
sched_clock_register(tc_sched_clock, 32, divided_rate);
|
|
|
|
|
2008-02-23 01:28:37 +00:00
|
|
|
return 0;
|
2013-10-02 12:35:20 +00:00
|
|
|
|
2013-10-02 12:35:41 +00:00
|
|
|
err_unregister_clksrc:
|
|
|
|
clocksource_unregister(&clksrc);
|
|
|
|
|
|
|
|
err_disable_t1:
|
2019-04-26 21:47:11 +00:00
|
|
|
if (bits != 32)
|
|
|
|
clk_disable_unprepare(tc.clk[1]);
|
2013-10-02 12:35:41 +00:00
|
|
|
|
2013-10-02 12:35:20 +00:00
|
|
|
err_disable_t0:
|
|
|
|
clk_disable_unprepare(t0_clk);
|
|
|
|
|
2019-04-26 21:47:11 +00:00
|
|
|
tcaddr = NULL;
|
|
|
|
|
2013-10-02 12:35:20 +00:00
|
|
|
return ret;
|
2008-02-23 01:28:37 +00:00
|
|
|
}
|
2019-04-26 21:47:11 +00:00
|
|
|
TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);
|