2019-07-01 04:25:56 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Definitions for the clocksource provided by the Hyper-V
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* hypervisor to guest VMs, as described in the Hyper-V Top
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* Level Functional Spec (TLFS).
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*
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* Copyright (C) 2019, Microsoft, Inc.
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*
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* Author: Michael Kelley <mikelley@microsoft.com>
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*/
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#ifndef __CLKSOURCE_HYPERV_TIMER_H
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#define __CLKSOURCE_HYPERV_TIMER_H
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2019-07-01 04:26:06 +00:00
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#include <linux/clocksource.h>
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#include <linux/math64.h>
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#include <asm/mshyperv.h>
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2019-07-01 04:25:56 +00:00
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#define HV_MAX_MAX_DELTA_TICKS 0xffffffff
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#define HV_MIN_DELTA_TICKS 1
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2021-07-14 00:01:46 +00:00
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#ifdef CONFIG_HYPERV_TIMER
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2019-07-01 04:25:56 +00:00
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/* Routines called by the VMbus driver */
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2021-03-02 21:38:22 +00:00
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extern int hv_stimer_alloc(bool have_percpu_irqs);
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x86/hyperv: Initialize clockevents earlier in CPU onlining
Hyper-V has historically initialized stimer-based clockevents late in the
process of onlining a CPU because clockevents depend on stimer
interrupts. In the original Hyper-V design, stimer interrupts generate a
VMbus message, so the VMbus machinery must be running first, and VMbus
can't be initialized until relatively late. On x86/64, LAPIC timer based
clockevents are used during early initialization before VMbus and
stimer-based clockevents are ready, and again during CPU offlining after
the stimer clockevents have been shut down.
Unfortunately, this design creates problems when offlining CPUs for
hibernation or other purposes. stimer-based clockevents are shut down
relatively early in the offlining process, so clockevents_unbind_device()
must be used to fallback to the LAPIC-based clockevents for the remainder
of the offlining process. Furthermore, the late initialization and early
shutdown of stimer-based clockevents doesn't work well on ARM64 since there
is no other timer like the LAPIC to fallback to. So CPU onlining and
offlining doesn't work properly.
Fix this by recognizing that stimer Direct Mode is the normal path for
newer versions of Hyper-V on x86/64, and the only path on other
architectures. With stimer Direct Mode, stimer interrupts don't require any
VMbus machinery. stimer clockevents can be initialized and shut down
consistent with how it is done for other clockevent devices. While the old
VMbus-based stimer interrupts must still be supported for backward
compatibility on x86, that mode of operation can be treated as legacy.
So add a new Hyper-V stimer entry in the CPU hotplug state list, and use
that new state when in Direct Mode. Update the Hyper-V clocksource driver
to allocate and initialize stimer clockevents earlier during boot. Update
Hyper-V initialization and the VMbus driver to use this new design. As a
result, the LAPIC timer is no longer used during boot or CPU
onlining/offlining and clockevents_unbind_device() is not called. But
retain the old design as a legacy implementation for older versions of
Hyper-V that don't support Direct Mode.
Signed-off-by: Michael Kelley <mikelley@microsoft.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Dexuan Cui <decui@microsoft.com>
Reviewed-by: Dexuan Cui <decui@microsoft.com>
Link: https://lkml.kernel.org/r/1573607467-9456-1-git-send-email-mikelley@microsoft.com
2019-11-13 01:11:49 +00:00
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extern int hv_stimer_cleanup(unsigned int cpu);
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extern void hv_stimer_legacy_init(unsigned int cpu, int sint);
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extern void hv_stimer_legacy_cleanup(unsigned int cpu);
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2019-07-01 04:25:56 +00:00
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extern void hv_stimer_global_cleanup(void);
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extern void hv_stimer0_isr(void);
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2019-07-01 04:26:06 +00:00
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extern void hv_init_clocksource(void);
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extern struct ms_hyperv_tsc_page *hv_get_tsc_page(void);
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static inline notrace u64
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hv_read_tsc_page_tsc(const struct ms_hyperv_tsc_page *tsc_pg, u64 *cur_tsc)
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{
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u64 scale, offset;
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u32 sequence;
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/*
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* The protocol for reading Hyper-V TSC page is specified in Hypervisor
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* Top-Level Functional Specification ver. 3.0 and above. To get the
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* reference time we must do the following:
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* - READ ReferenceTscSequence
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* A special '0' value indicates the time source is unreliable and we
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* need to use something else. The currently published specification
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* versions (up to 4.0b) contain a mistake and wrongly claim '-1'
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* instead of '0' as the special value, see commit c35b82ef0294.
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* - ReferenceTime =
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* ((RDTSC() * ReferenceTscScale) >> 64) + ReferenceTscOffset
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* - READ ReferenceTscSequence again. In case its value has changed
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* since our first reading we need to discard ReferenceTime and repeat
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* the whole sequence as the hypervisor was updating the page in
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* between.
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*/
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do {
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sequence = READ_ONCE(tsc_pg->tsc_sequence);
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if (!sequence)
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return U64_MAX;
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/*
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* Make sure we read sequence before we read other values from
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* TSC page.
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*/
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smp_rmb();
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scale = READ_ONCE(tsc_pg->tsc_scale);
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offset = READ_ONCE(tsc_pg->tsc_offset);
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*cur_tsc = hv_get_raw_timer();
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/*
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* Make sure we read sequence after we read all other values
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* from TSC page.
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*/
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smp_rmb();
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} while (READ_ONCE(tsc_pg->tsc_sequence) != sequence);
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return mul_u64_u64_shr(*cur_tsc, scale, 64) + offset;
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}
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static inline notrace u64
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hv_read_tsc_page(const struct ms_hyperv_tsc_page *tsc_pg)
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{
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u64 cur_tsc;
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return hv_read_tsc_page_tsc(tsc_pg, &cur_tsc);
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}
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2019-08-22 08:36:30 +00:00
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#else /* CONFIG_HYPERV_TIMER */
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2019-07-01 04:26:06 +00:00
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static inline struct ms_hyperv_tsc_page *hv_get_tsc_page(void)
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{
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return NULL;
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}
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static inline u64 hv_read_tsc_page_tsc(const struct ms_hyperv_tsc_page *tsc_pg,
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u64 *cur_tsc)
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{
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return U64_MAX;
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}
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2021-07-14 00:01:46 +00:00
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static inline int hv_stimer_cleanup(unsigned int cpu) { return 0; }
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static inline void hv_stimer_legacy_init(unsigned int cpu, int sint) {}
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static inline void hv_stimer_legacy_cleanup(unsigned int cpu) {}
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static inline void hv_stimer_global_cleanup(void) {}
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static inline void hv_stimer0_isr(void) {}
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2019-08-22 08:36:30 +00:00
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#endif /* CONFIG_HYPERV_TIMER */
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2019-07-01 04:26:06 +00:00
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2019-07-01 04:25:56 +00:00
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#endif
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