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71 lines
2.4 KiB
C
71 lines
2.4 KiB
C
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/**
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*
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* Fixes and workaround for Octeon chip errata. This file
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* contains functions called by cvmx-helper to workaround known
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* chip errata. For the most part, code doesn't need to call
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* these functions directly.
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*
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*/
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-helper-jtag.h>
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/**
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* Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
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* 1 doesn't work properly. The following code disables 2nd order
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* CDR for the specified QLM.
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*
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* @qlm: QLM to disable 2nd order CDR for.
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*/
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void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
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{
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int lane;
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cvmx_helper_qlm_jtag_init();
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/* We need to load all four lanes of the QLM, a total of 1072 bits */
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for (lane = 0; lane < 4; lane++) {
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/*
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* Each lane has 268 bits. We need to set
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* cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
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* 1. All other bits are zero. Bits go in LSB first,
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* so start off with the zeros for bits <63:0>.
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*/
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cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
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/* cfg_cdr_incx<67:64>=3 */
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cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
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/* Zeros for bits <76:68> */
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cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
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/* cfg_cdr_secord<77>=1 */
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cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
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/* Zeros for bits <267:78> */
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cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
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}
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cvmx_helper_qlm_jtag_update(qlm);
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}
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