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73 lines
3.0 KiB
Plaintext
73 lines
3.0 KiB
Plaintext
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* QEMU Firmware Configuration bindings for ARM
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QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets
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provide the following Firmware Configuration interface on the "virt" machine
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type:
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- A write-only, 16-bit wide selector (or control) register,
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- a read-write, 64-bit wide data register.
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QEMU exposes the control and data register to ARM guests as memory mapped
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registers; their location is communicated to the guest's UEFI firmware in the
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DTB that QEMU places at the bottom of the guest's DRAM.
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The guest writes a selector value (a key) to the selector register, and then
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can read the corresponding data (produced by QEMU) via the data register. If
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the selected entry is writable, the guest can rewrite it through the data
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register.
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The selector register takes keys in big endian byte order.
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The data register allows accesses with 8, 16, 32 and 64-bit width (only at
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offset 0 of the register). Accesses larger than a byte are interpreted as
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arrays, bundled together only for better performance. The bytes constituting
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such a word, in increasing address order, correspond to the bytes that would
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have been transferred by byte-wide accesses in chronological order.
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The interface allows guest firmware to download various parameters and blobs
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that affect how the firmware works and what tables it installs for the guest
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OS. For example, boot order of devices, ACPI tables, SMBIOS tables, kernel and
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initrd images for direct kernel booting, virtual machine UUID, SMP information,
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virtual NUMA topology, and so on.
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The authoritative registry of the valid selector values and their meanings is
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the QEMU source code; the structure of the data blobs corresponding to the
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individual key values is also defined in the QEMU source code.
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The presence of the registers can be verified by selecting the "signature" blob
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with key 0x0000, and reading four bytes from the data register. The returned
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signature is "QEMU".
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The outermost protocol (involving the write / read sequences of the control and
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data registers) is expected to be versioned, and/or described by feature bits.
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The interface revision / feature bitmap can be retrieved with key 0x0001. The
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blob to be read from the data register has size 4, and it is to be interpreted
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as a uint32_t value in little endian byte order. The current value
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(corresponding to the above outer protocol) is zero.
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The guest kernel is not expected to use these registers (although it is
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certainly allowed to); the device tree bindings are documented here because
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this is where device tree bindings reside in general.
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Required properties:
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- compatible: "qemu,fw-cfg-mmio".
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- reg: the MMIO region used by the device.
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* Bytes 0x0 to 0x7 cover the data register.
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* Bytes 0x8 to 0x9 cover the selector register.
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* Further registers may be appended to the region in case of future interface
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revisions / feature bits.
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Example:
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/ {
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#size-cells = <0x2>;
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#address-cells = <0x2>;
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fw-cfg@9020000 {
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compatible = "qemu,fw-cfg-mmio";
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reg = <0x0 0x9020000 0x0 0xa>;
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};
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};
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