2009-09-24 00:46:15 +00:00
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/*
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* Copyright (c) 2005-2009 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*
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* Linux driver for Brocade Fibre Channel Host Bus Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <bfa.h>
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2010-03-04 01:43:09 +00:00
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#include <bfi/bfi_ctreg.h>
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2009-09-24 00:46:15 +00:00
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#include <bfa_port_priv.h>
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#include <bfa_intr_priv.h>
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#include <cs/bfa_debug.h>
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BFA_TRC_FILE(HAL, INTR);
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static void
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bfa_msix_errint(struct bfa_s *bfa, u32 intr)
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{
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bfa_ioc_error_isr(&bfa->ioc);
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}
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static void
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bfa_msix_lpu(struct bfa_s *bfa)
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{
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bfa_ioc_mbox_isr(&bfa->ioc);
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}
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2010-03-06 03:37:09 +00:00
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static void
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bfa_reqq_resume(struct bfa_s *bfa, int qid)
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{
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struct list_head *waitq, *qe, *qen;
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struct bfa_reqq_wait_s *wqe;
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waitq = bfa_reqq(bfa, qid);
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list_for_each_safe(qe, qen, waitq) {
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/**
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* Callback only as long as there is room in request queue
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*/
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if (bfa_reqq_full(bfa, qid))
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break;
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list_del(qe);
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wqe = (struct bfa_reqq_wait_s *) qe;
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wqe->qresume(wqe->cbarg);
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}
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}
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2009-09-24 00:46:15 +00:00
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void
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bfa_msix_all(struct bfa_s *bfa, int vec)
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{
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bfa_intx(bfa);
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}
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/**
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* hal_intr_api
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*/
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bfa_boolean_t
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bfa_intx(struct bfa_s *bfa)
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{
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u32 intr, qintr;
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int queue;
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intr = bfa_reg_read(bfa->iocfc.bfa_regs.intr_status);
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if (!intr)
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return BFA_FALSE;
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/**
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* RME completion queue interrupt
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*/
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qintr = intr & __HFN_INT_RME_MASK;
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bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, qintr);
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2009-09-25 19:29:54 +00:00
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for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
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2009-09-24 00:46:15 +00:00
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if (intr & (__HFN_INT_RME_Q0 << queue))
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bfa_msix_rspq(bfa, queue & (BFI_IOC_MAX_CQS - 1));
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}
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intr &= ~qintr;
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if (!intr)
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return BFA_TRUE;
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/**
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* CPE completion queue interrupt
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*/
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qintr = intr & __HFN_INT_CPE_MASK;
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bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, qintr);
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for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
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if (intr & (__HFN_INT_CPE_Q0 << queue))
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bfa_msix_reqq(bfa, queue & (BFI_IOC_MAX_CQS - 1));
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}
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intr &= ~qintr;
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if (!intr)
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return BFA_TRUE;
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bfa_msix_lpu_err(bfa, intr);
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return BFA_TRUE;
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}
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void
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bfa_isr_enable(struct bfa_s *bfa)
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{
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u32 intr_unmask;
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int pci_func = bfa_ioc_pcifn(&bfa->ioc);
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bfa_trc(bfa, pci_func);
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bfa_msix_install(bfa);
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intr_unmask = (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 |
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2010-03-04 01:43:09 +00:00
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__HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS |
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__HFN_INT_LL_HALT);
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2009-09-24 00:46:15 +00:00
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if (pci_func == 0)
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intr_unmask |= (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 |
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__HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 |
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__HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 |
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__HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 |
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__HFN_INT_MBOX_LPU0);
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else
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intr_unmask |= (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 |
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__HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 |
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__HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 |
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__HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
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__HFN_INT_MBOX_LPU1);
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bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, intr_unmask);
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bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, ~intr_unmask);
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bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0);
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}
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void
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bfa_isr_disable(struct bfa_s *bfa)
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{
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bfa_isr_mode_set(bfa, BFA_FALSE);
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bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, -1L);
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bfa_msix_uninstall(bfa);
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}
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void
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bfa_msix_reqq(struct bfa_s *bfa, int qid)
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{
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2010-03-06 03:37:09 +00:00
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struct list_head *waitq;
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2009-09-24 00:46:15 +00:00
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qid &= (BFI_IOC_MAX_CQS - 1);
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2010-03-06 03:37:09 +00:00
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bfa->iocfc.hwif.hw_reqq_ack(bfa, qid);
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2009-09-24 00:46:15 +00:00
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2010-03-06 03:37:09 +00:00
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/**
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* Resume any pending requests in the corresponding reqq.
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*/
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waitq = bfa_reqq(bfa, qid);
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if (!list_empty(waitq))
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bfa_reqq_resume(bfa, qid);
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2009-09-24 00:46:15 +00:00
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}
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void
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bfa_isr_unhandled(struct bfa_s *bfa, struct bfi_msg_s *m)
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{
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bfa_trc(bfa, m->mhdr.msg_class);
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bfa_trc(bfa, m->mhdr.msg_id);
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bfa_trc(bfa, m->mhdr.mtag.i2htok);
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bfa_assert(0);
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bfa_trc_stop(bfa->trcmod);
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}
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void
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2010-03-06 03:37:09 +00:00
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bfa_msix_rspq(struct bfa_s *bfa, int qid)
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2009-09-24 00:46:15 +00:00
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{
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2010-03-06 03:37:09 +00:00
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struct bfi_msg_s *m;
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u32 pi, ci;
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struct list_head *waitq;
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2009-09-24 00:46:15 +00:00
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2010-03-06 03:37:09 +00:00
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bfa_trc_fp(bfa, qid);
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2009-09-24 00:46:15 +00:00
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2010-03-06 03:37:09 +00:00
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qid &= (BFI_IOC_MAX_CQS - 1);
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2009-09-24 00:46:15 +00:00
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2010-03-06 03:37:09 +00:00
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bfa->iocfc.hwif.hw_rspq_ack(bfa, qid);
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2009-09-24 00:46:15 +00:00
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2010-03-06 03:37:09 +00:00
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ci = bfa_rspq_ci(bfa, qid);
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pi = bfa_rspq_pi(bfa, qid);
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2009-09-24 00:46:15 +00:00
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bfa_trc_fp(bfa, ci);
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bfa_trc_fp(bfa, pi);
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if (bfa->rme_process) {
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while (ci != pi) {
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2010-03-06 03:37:09 +00:00
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m = bfa_rspq_elem(bfa, qid, ci);
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2009-09-24 00:46:15 +00:00
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bfa_assert_fp(m->mhdr.msg_class < BFI_MC_MAX);
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bfa_isrs[m->mhdr.msg_class] (bfa, m);
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CQ_INCR(ci, bfa->iocfc.cfg.drvcfg.num_rspq_elems);
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}
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}
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/**
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* update CI
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*/
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2010-03-06 03:37:09 +00:00
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bfa_rspq_ci(bfa, qid) = pi;
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bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ci[qid], pi);
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2009-09-24 00:46:15 +00:00
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bfa_os_mmiowb();
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2010-03-06 03:37:09 +00:00
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/**
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* Resume any pending requests in the corresponding reqq.
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*/
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waitq = bfa_reqq(bfa, qid);
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if (!list_empty(waitq))
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bfa_reqq_resume(bfa, qid);
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2009-09-24 00:46:15 +00:00
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}
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void
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bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
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{
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2010-03-06 03:34:44 +00:00
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u32 intr, curr_value;
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2009-09-24 00:46:15 +00:00
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intr = bfa_reg_read(bfa->iocfc.bfa_regs.intr_status);
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if (intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1))
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bfa_msix_lpu(bfa);
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2010-03-06 03:34:44 +00:00
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intr &= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 |
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__HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT);
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if (intr) {
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if (intr & __HFN_INT_LL_HALT) {
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/**
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* If LL_HALT bit is set then FW Init Halt LL Port
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* Register needs to be cleared as well so Interrupt
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* Status Register will be cleared.
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*/
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curr_value = bfa_reg_read(bfa->ioc.ioc_regs.ll_halt);
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curr_value &= ~__FW_INIT_HALT_P;
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bfa_reg_write(bfa->ioc.ioc_regs.ll_halt, curr_value);
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}
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if (intr & __HFN_INT_ERR_PSS) {
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/**
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* ERR_PSS bit needs to be cleared as well in case
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* interrups are shared so driver's interrupt handler is
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* still called eventhough it is already masked out.
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*/
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curr_value = bfa_reg_read(
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bfa->ioc.ioc_regs.pss_err_status_reg);
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curr_value &= __PSS_ERR_STATUS_SET;
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bfa_reg_write(bfa->ioc.ioc_regs.pss_err_status_reg,
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curr_value);
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}
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bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, intr);
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2009-09-24 00:46:15 +00:00
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bfa_msix_errint(bfa, intr);
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2010-03-06 03:34:44 +00:00
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}
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2009-09-24 00:46:15 +00:00
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}
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void
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bfa_isr_bind(enum bfi_mclass mc, bfa_isr_func_t isr_func)
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{
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bfa_isrs[mc] = isr_func;
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}
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