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856 lines
22 KiB
C
856 lines
22 KiB
C
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/* $Id: pci_iommu.c,v 1.17 2001/12/17 07:05:09 davem Exp $
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* pci_iommu.c: UltraSparc PCI controller IOM/STC support.
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*
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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* Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/pbm.h>
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#include "iommu_common.h"
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#define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
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((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
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/* Accessing IOMMU and Streaming Buffer registers.
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* REG parameter is a physical address. All registers
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* are 64-bits in size.
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*/
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#define pci_iommu_read(__reg) \
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({ u64 __ret; \
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__asm__ __volatile__("ldxa [%1] %2, %0" \
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: "=r" (__ret) \
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: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
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: "memory"); \
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__ret; \
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})
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#define pci_iommu_write(__reg, __val) \
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__asm__ __volatile__("stxa %0, [%1] %2" \
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: /* no outputs */ \
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: "r" (__val), "r" (__reg), \
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"i" (ASI_PHYS_BYPASS_EC_E))
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/* Must be invoked under the IOMMU lock. */
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static void __iommu_flushall(struct pci_iommu *iommu)
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{
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unsigned long tag;
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int entry;
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tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
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for (entry = 0; entry < 16; entry++) {
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pci_iommu_write(tag, 0);
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tag += 8;
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}
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/* Ensure completion of previous PIO writes. */
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(void) pci_iommu_read(iommu->write_complete_reg);
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/* Now update everyone's flush point. */
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for (entry = 0; entry < PBM_NCLUSTERS; entry++) {
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iommu->alloc_info[entry].flush =
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iommu->alloc_info[entry].next;
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}
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}
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#define IOPTE_CONSISTENT(CTX) \
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(IOPTE_VALID | IOPTE_CACHE | \
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(((CTX) << 47) & IOPTE_CONTEXT))
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#define IOPTE_STREAMING(CTX) \
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(IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
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/* Existing mappings are never marked invalid, instead they
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* are pointed to a dummy page.
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*/
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#define IOPTE_IS_DUMMY(iommu, iopte) \
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((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
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static void inline iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
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{
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unsigned long val = iopte_val(*iopte);
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val &= ~IOPTE_PAGE;
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val |= iommu->dummy_page_pa;
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iopte_val(*iopte) = val;
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}
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void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize)
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{
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int i;
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tsbsize /= sizeof(iopte_t);
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for (i = 0; i < tsbsize; i++)
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iopte_make_dummy(iommu, &iommu->page_table[i]);
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}
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static iopte_t *alloc_streaming_cluster(struct pci_iommu *iommu, unsigned long npages)
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{
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iopte_t *iopte, *limit, *first;
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unsigned long cnum, ent, flush_point;
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cnum = 0;
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while ((1UL << cnum) < npages)
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cnum++;
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iopte = (iommu->page_table +
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(cnum << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
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if (cnum == 0)
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limit = (iommu->page_table +
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iommu->lowest_consistent_map);
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else
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limit = (iopte +
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(1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
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iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
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flush_point = iommu->alloc_info[cnum].flush;
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first = iopte;
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for (;;) {
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if (IOPTE_IS_DUMMY(iommu, iopte)) {
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if ((iopte + (1 << cnum)) >= limit)
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ent = 0;
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else
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ent = ent + 1;
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iommu->alloc_info[cnum].next = ent;
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if (ent == flush_point)
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__iommu_flushall(iommu);
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break;
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}
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iopte += (1 << cnum);
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ent++;
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if (iopte >= limit) {
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iopte = (iommu->page_table +
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(cnum <<
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(iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
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ent = 0;
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}
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if (ent == flush_point)
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__iommu_flushall(iommu);
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if (iopte == first)
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goto bad;
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}
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/* I've got your streaming cluster right here buddy boy... */
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return iopte;
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bad:
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printk(KERN_EMERG "pci_iommu: alloc_streaming_cluster of npages(%ld) failed!\n",
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npages);
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return NULL;
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}
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static void free_streaming_cluster(struct pci_iommu *iommu, dma_addr_t base,
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unsigned long npages, unsigned long ctx)
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{
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unsigned long cnum, ent;
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cnum = 0;
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while ((1UL << cnum) < npages)
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cnum++;
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ent = (base << (32 - IO_PAGE_SHIFT + PBM_LOGCLUSTERS - iommu->page_table_sz_bits))
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>> (32 + PBM_LOGCLUSTERS + cnum - iommu->page_table_sz_bits);
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/* If the global flush might not have caught this entry,
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* adjust the flush point such that we will flush before
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* ever trying to reuse it.
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*/
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#define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
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if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
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iommu->alloc_info[cnum].flush = ent;
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#undef between
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}
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/* We allocate consistent mappings from the end of cluster zero. */
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static iopte_t *alloc_consistent_cluster(struct pci_iommu *iommu, unsigned long npages)
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{
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iopte_t *iopte;
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iopte = iommu->page_table + (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS));
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while (iopte > iommu->page_table) {
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iopte--;
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if (IOPTE_IS_DUMMY(iommu, iopte)) {
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unsigned long tmp = npages;
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while (--tmp) {
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iopte--;
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if (!IOPTE_IS_DUMMY(iommu, iopte))
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break;
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}
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if (tmp == 0) {
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u32 entry = (iopte - iommu->page_table);
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if (entry < iommu->lowest_consistent_map)
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iommu->lowest_consistent_map = entry;
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return iopte;
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}
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}
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}
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return NULL;
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}
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/* Allocate and map kernel buffer of size SIZE using consistent mode
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* DMA for PCI device PDEV. Return non-NULL cpu-side address if
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* successful and set *DMA_ADDRP to the PCI side dma address.
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*/
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void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, first_page, ctx;
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void *ret;
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int npages;
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size = IO_PAGE_ALIGN(size);
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order = get_order(size);
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if (order >= 10)
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return NULL;
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first_page = __get_free_pages(GFP_ATOMIC, order);
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if (first_page == 0UL)
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return NULL;
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memset((char *)first_page, 0, PAGE_SIZE << order);
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
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if (iopte == NULL) {
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spin_unlock_irqrestore(&iommu->lock, flags);
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free_pages(first_page, order);
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return NULL;
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}
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*dma_addrp = (iommu->page_table_map_base +
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((iopte - iommu->page_table) << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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npages = size >> IO_PAGE_SHIFT;
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu->iommu_cur_ctx++;
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first_page = __pa(first_page);
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while (npages--) {
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iopte_val(*iopte) = (IOPTE_CONSISTENT(ctx) |
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IOPTE_WRITE |
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(first_page & IOPTE_PAGE));
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iopte++;
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first_page += IO_PAGE_SIZE;
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}
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{
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int i;
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u32 daddr = *dma_addrp;
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npages = size >> IO_PAGE_SHIFT;
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for (i = 0; i < npages; i++) {
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pci_iommu_write(iommu->iommu_flush, daddr);
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daddr += IO_PAGE_SIZE;
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}
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}
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spin_unlock_irqrestore(&iommu->lock, flags);
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return ret;
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}
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/* Free and unmap a consistent DMA translation. */
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void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, npages, i, ctx;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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iopte = iommu->page_table +
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((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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if ((iopte - iommu->page_table) ==
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iommu->lowest_consistent_map) {
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iopte_t *walk = iopte + npages;
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iopte_t *limit;
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limit = (iommu->page_table +
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(1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
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while (walk < limit) {
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if (!IOPTE_IS_DUMMY(iommu, walk))
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break;
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walk++;
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}
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iommu->lowest_consistent_map =
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(walk - iommu->page_table);
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}
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/* Data for consistent mappings cannot enter the streaming
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* buffers, so we only need to update the TSB. We flush
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* the IOMMU here as well to prevent conflicts with the
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* streaming mapping deferred tlb flush scheme.
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*/
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
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for (i = 0; i < npages; i++, iopte++)
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iopte_make_dummy(iommu, iopte);
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if (iommu->iommu_ctxflush) {
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pci_iommu_write(iommu->iommu_ctxflush, ctx);
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} else {
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for (i = 0; i < npages; i++) {
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u32 daddr = dvma + (i << IO_PAGE_SHIFT);
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pci_iommu_write(iommu->iommu_flush, daddr);
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}
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}
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spin_unlock_irqrestore(&iommu->lock, flags);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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}
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/* Map a single buffer at PTR of SZ bytes for PCI DMA
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* in streaming mode.
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*/
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dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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struct pci_strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr, ctx;
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u32 bus_addr, ret;
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unsigned long iopte_protection;
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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strbuf = &pcp->pbm->stc;
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if (direction == PCI_DMA_NONE)
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BUG();
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oaddr = (unsigned long)ptr;
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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spin_lock_irqsave(&iommu->lock, flags);
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base = alloc_streaming_cluster(iommu, npages);
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if (base == NULL)
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goto bad;
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bus_addr = (iommu->page_table_map_base +
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((base - iommu->page_table) << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu->iommu_cur_ctx++;
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if (strbuf->strbuf_enabled)
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iopte_protection = IOPTE_STREAMING(ctx);
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else
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iopte_protection = IOPTE_CONSISTENT(ctx);
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if (direction != PCI_DMA_TODEVICE)
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iopte_protection |= IOPTE_WRITE;
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for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
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iopte_val(*base) = iopte_protection | base_paddr;
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spin_unlock_irqrestore(&iommu->lock, flags);
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return ret;
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bad:
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spin_unlock_irqrestore(&iommu->lock, flags);
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return PCI_DMA_ERROR_CODE;
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}
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/* Unmap a single streaming mode DMA translation. */
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void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
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{
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struct pcidev_cookie *pcp;
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struct pci_iommu *iommu;
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struct pci_strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, npages, i, ctx;
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if (direction == PCI_DMA_NONE)
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BUG();
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pcp = pdev->sysdata;
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iommu = pcp->pbm->iommu;
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strbuf = &pcp->pbm->stc;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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base = iommu->page_table +
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((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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#ifdef DEBUG_PCI_IOMMU
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if (IOPTE_IS_DUMMY(iommu, base))
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printk("pci_unmap_single called on non-mapped region %08x,%08x from %016lx\n",
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bus_addr, sz, __builtin_return_address(0));
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#endif
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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/* Record the context, if any. */
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
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/* Step 1: Kick data out of streaming buffers if necessary. */
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|
if (strbuf->strbuf_enabled) {
|
||
|
u32 vaddr = bus_addr;
|
||
|
|
||
|
PCI_STC_FLUSHFLAG_INIT(strbuf);
|
||
|
if (strbuf->strbuf_ctxflush &&
|
||
|
iommu->iommu_ctxflush) {
|
||
|
unsigned long matchreg, flushreg;
|
||
|
|
||
|
flushreg = strbuf->strbuf_ctxflush;
|
||
|
matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
|
||
|
do {
|
||
|
pci_iommu_write(flushreg, ctx);
|
||
|
} while(((long)pci_iommu_read(matchreg)) < 0L);
|
||
|
} else {
|
||
|
for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
|
||
|
pci_iommu_write(strbuf->strbuf_pflush, vaddr);
|
||
|
}
|
||
|
|
||
|
pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
|
||
|
(void) pci_iommu_read(iommu->write_complete_reg);
|
||
|
while (!PCI_STC_FLUSHFLAG_SET(strbuf))
|
||
|
membar("#LoadLoad");
|
||
|
}
|
||
|
|
||
|
/* Step 2: Clear out first TSB entry. */
|
||
|
iopte_make_dummy(iommu, base);
|
||
|
|
||
|
free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
|
||
|
npages, ctx);
|
||
|
|
||
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
||
|
}
|
||
|
|
||
|
#define SG_ENT_PHYS_ADDRESS(SG) \
|
||
|
(__pa(page_address((SG)->page)) + (SG)->offset)
|
||
|
|
||
|
static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
|
||
|
int nused, int nelems, unsigned long iopte_protection)
|
||
|
{
|
||
|
struct scatterlist *dma_sg = sg;
|
||
|
struct scatterlist *sg_end = sg + nelems;
|
||
|
int i;
|
||
|
|
||
|
for (i = 0; i < nused; i++) {
|
||
|
unsigned long pteval = ~0UL;
|
||
|
u32 dma_npages;
|
||
|
|
||
|
dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
|
||
|
dma_sg->dma_length +
|
||
|
((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
|
||
|
do {
|
||
|
unsigned long offset;
|
||
|
signed int len;
|
||
|
|
||
|
/* If we are here, we know we have at least one
|
||
|
* more page to map. So walk forward until we
|
||
|
* hit a page crossing, and begin creating new
|
||
|
* mappings from that spot.
|
||
|
*/
|
||
|
for (;;) {
|
||
|
unsigned long tmp;
|
||
|
|
||
|
tmp = SG_ENT_PHYS_ADDRESS(sg);
|
||
|
len = sg->length;
|
||
|
if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
|
||
|
pteval = tmp & IO_PAGE_MASK;
|
||
|
offset = tmp & (IO_PAGE_SIZE - 1UL);
|
||
|
break;
|
||
|
}
|
||
|
if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
|
||
|
pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
|
||
|
offset = 0UL;
|
||
|
len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
|
||
|
break;
|
||
|
}
|
||
|
sg++;
|
||
|
}
|
||
|
|
||
|
pteval = iopte_protection | (pteval & IOPTE_PAGE);
|
||
|
while (len > 0) {
|
||
|
*iopte++ = __iopte(pteval);
|
||
|
pteval += IO_PAGE_SIZE;
|
||
|
len -= (IO_PAGE_SIZE - offset);
|
||
|
offset = 0;
|
||
|
dma_npages--;
|
||
|
}
|
||
|
|
||
|
pteval = (pteval & IOPTE_PAGE) + len;
|
||
|
sg++;
|
||
|
|
||
|
/* Skip over any tail mappings we've fully mapped,
|
||
|
* adjusting pteval along the way. Stop when we
|
||
|
* detect a page crossing event.
|
||
|
*/
|
||
|
while (sg < sg_end &&
|
||
|
(pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
|
||
|
(pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
|
||
|
((pteval ^
|
||
|
(SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
|
||
|
pteval += sg->length;
|
||
|
sg++;
|
||
|
}
|
||
|
if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
|
||
|
pteval = ~0UL;
|
||
|
} while (dma_npages != 0);
|
||
|
dma_sg++;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* Map a set of buffers described by SGLIST with NELEMS array
|
||
|
* elements in streaming mode for PCI DMA.
|
||
|
* When making changes here, inspect the assembly output. I was having
|
||
|
* hard time to kepp this routine out of using stack slots for holding variables.
|
||
|
*/
|
||
|
int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
|
||
|
{
|
||
|
struct pcidev_cookie *pcp;
|
||
|
struct pci_iommu *iommu;
|
||
|
struct pci_strbuf *strbuf;
|
||
|
unsigned long flags, ctx, npages, iopte_protection;
|
||
|
iopte_t *base;
|
||
|
u32 dma_base;
|
||
|
struct scatterlist *sgtmp;
|
||
|
int used;
|
||
|
|
||
|
/* Fast path single entry scatterlists. */
|
||
|
if (nelems == 1) {
|
||
|
sglist->dma_address =
|
||
|
pci_map_single(pdev,
|
||
|
(page_address(sglist->page) + sglist->offset),
|
||
|
sglist->length, direction);
|
||
|
sglist->dma_length = sglist->length;
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
pcp = pdev->sysdata;
|
||
|
iommu = pcp->pbm->iommu;
|
||
|
strbuf = &pcp->pbm->stc;
|
||
|
|
||
|
if (direction == PCI_DMA_NONE)
|
||
|
BUG();
|
||
|
|
||
|
/* Step 1: Prepare scatter list. */
|
||
|
|
||
|
npages = prepare_sg(sglist, nelems);
|
||
|
|
||
|
/* Step 2: Allocate a cluster. */
|
||
|
|
||
|
spin_lock_irqsave(&iommu->lock, flags);
|
||
|
|
||
|
base = alloc_streaming_cluster(iommu, npages);
|
||
|
if (base == NULL)
|
||
|
goto bad;
|
||
|
dma_base = iommu->page_table_map_base + ((base - iommu->page_table) << IO_PAGE_SHIFT);
|
||
|
|
||
|
/* Step 3: Normalize DMA addresses. */
|
||
|
used = nelems;
|
||
|
|
||
|
sgtmp = sglist;
|
||
|
while (used && sgtmp->dma_length) {
|
||
|
sgtmp->dma_address += dma_base;
|
||
|
sgtmp++;
|
||
|
used--;
|
||
|
}
|
||
|
used = nelems - used;
|
||
|
|
||
|
/* Step 4: Choose a context if necessary. */
|
||
|
ctx = 0;
|
||
|
if (iommu->iommu_ctxflush)
|
||
|
ctx = iommu->iommu_cur_ctx++;
|
||
|
|
||
|
/* Step 5: Create the mappings. */
|
||
|
if (strbuf->strbuf_enabled)
|
||
|
iopte_protection = IOPTE_STREAMING(ctx);
|
||
|
else
|
||
|
iopte_protection = IOPTE_CONSISTENT(ctx);
|
||
|
if (direction != PCI_DMA_TODEVICE)
|
||
|
iopte_protection |= IOPTE_WRITE;
|
||
|
fill_sg (base, sglist, used, nelems, iopte_protection);
|
||
|
#ifdef VERIFY_SG
|
||
|
verify_sglist(sglist, nelems, base, npages);
|
||
|
#endif
|
||
|
|
||
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
||
|
|
||
|
return used;
|
||
|
|
||
|
bad:
|
||
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
||
|
return PCI_DMA_ERROR_CODE;
|
||
|
}
|
||
|
|
||
|
/* Unmap a set of streaming mode DMA translations. */
|
||
|
void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
|
||
|
{
|
||
|
struct pcidev_cookie *pcp;
|
||
|
struct pci_iommu *iommu;
|
||
|
struct pci_strbuf *strbuf;
|
||
|
iopte_t *base;
|
||
|
unsigned long flags, ctx, i, npages;
|
||
|
u32 bus_addr;
|
||
|
|
||
|
if (direction == PCI_DMA_NONE)
|
||
|
BUG();
|
||
|
|
||
|
pcp = pdev->sysdata;
|
||
|
iommu = pcp->pbm->iommu;
|
||
|
strbuf = &pcp->pbm->stc;
|
||
|
|
||
|
bus_addr = sglist->dma_address & IO_PAGE_MASK;
|
||
|
|
||
|
for (i = 1; i < nelems; i++)
|
||
|
if (sglist[i].dma_length == 0)
|
||
|
break;
|
||
|
i--;
|
||
|
npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - bus_addr) >> IO_PAGE_SHIFT;
|
||
|
|
||
|
base = iommu->page_table +
|
||
|
((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
||
|
|
||
|
#ifdef DEBUG_PCI_IOMMU
|
||
|
if (IOPTE_IS_DUMMY(iommu, base))
|
||
|
printk("pci_unmap_sg called on non-mapped region %016lx,%d from %016lx\n", sglist->dma_address, nelems, __builtin_return_address(0));
|
||
|
#endif
|
||
|
|
||
|
spin_lock_irqsave(&iommu->lock, flags);
|
||
|
|
||
|
/* Record the context, if any. */
|
||
|
ctx = 0;
|
||
|
if (iommu->iommu_ctxflush)
|
||
|
ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
|
||
|
|
||
|
/* Step 1: Kick data out of streaming buffers if necessary. */
|
||
|
if (strbuf->strbuf_enabled) {
|
||
|
u32 vaddr = (u32) bus_addr;
|
||
|
|
||
|
PCI_STC_FLUSHFLAG_INIT(strbuf);
|
||
|
if (strbuf->strbuf_ctxflush &&
|
||
|
iommu->iommu_ctxflush) {
|
||
|
unsigned long matchreg, flushreg;
|
||
|
|
||
|
flushreg = strbuf->strbuf_ctxflush;
|
||
|
matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
|
||
|
do {
|
||
|
pci_iommu_write(flushreg, ctx);
|
||
|
} while(((long)pci_iommu_read(matchreg)) < 0L);
|
||
|
} else {
|
||
|
for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
|
||
|
pci_iommu_write(strbuf->strbuf_pflush, vaddr);
|
||
|
}
|
||
|
|
||
|
pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
|
||
|
(void) pci_iommu_read(iommu->write_complete_reg);
|
||
|
while (!PCI_STC_FLUSHFLAG_SET(strbuf))
|
||
|
membar("#LoadLoad");
|
||
|
}
|
||
|
|
||
|
/* Step 2: Clear out first TSB entry. */
|
||
|
iopte_make_dummy(iommu, base);
|
||
|
|
||
|
free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
|
||
|
npages, ctx);
|
||
|
|
||
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
||
|
}
|
||
|
|
||
|
/* Make physical memory consistent for a single
|
||
|
* streaming mode DMA translation after a transfer.
|
||
|
*/
|
||
|
void pci_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
|
||
|
{
|
||
|
struct pcidev_cookie *pcp;
|
||
|
struct pci_iommu *iommu;
|
||
|
struct pci_strbuf *strbuf;
|
||
|
unsigned long flags, ctx, npages;
|
||
|
|
||
|
pcp = pdev->sysdata;
|
||
|
iommu = pcp->pbm->iommu;
|
||
|
strbuf = &pcp->pbm->stc;
|
||
|
|
||
|
if (!strbuf->strbuf_enabled)
|
||
|
return;
|
||
|
|
||
|
spin_lock_irqsave(&iommu->lock, flags);
|
||
|
|
||
|
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
|
||
|
npages >>= IO_PAGE_SHIFT;
|
||
|
bus_addr &= IO_PAGE_MASK;
|
||
|
|
||
|
/* Step 1: Record the context, if any. */
|
||
|
ctx = 0;
|
||
|
if (iommu->iommu_ctxflush &&
|
||
|
strbuf->strbuf_ctxflush) {
|
||
|
iopte_t *iopte;
|
||
|
|
||
|
iopte = iommu->page_table +
|
||
|
((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
|
||
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
||
|
}
|
||
|
|
||
|
/* Step 2: Kick data out of streaming buffers. */
|
||
|
PCI_STC_FLUSHFLAG_INIT(strbuf);
|
||
|
if (iommu->iommu_ctxflush &&
|
||
|
strbuf->strbuf_ctxflush) {
|
||
|
unsigned long matchreg, flushreg;
|
||
|
|
||
|
flushreg = strbuf->strbuf_ctxflush;
|
||
|
matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
|
||
|
do {
|
||
|
pci_iommu_write(flushreg, ctx);
|
||
|
} while(((long)pci_iommu_read(matchreg)) < 0L);
|
||
|
} else {
|
||
|
unsigned long i;
|
||
|
|
||
|
for (i = 0; i < npages; i++, bus_addr += IO_PAGE_SIZE)
|
||
|
pci_iommu_write(strbuf->strbuf_pflush, bus_addr);
|
||
|
}
|
||
|
|
||
|
/* Step 3: Perform flush synchronization sequence. */
|
||
|
pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
|
||
|
(void) pci_iommu_read(iommu->write_complete_reg);
|
||
|
while (!PCI_STC_FLUSHFLAG_SET(strbuf))
|
||
|
membar("#LoadLoad");
|
||
|
|
||
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
||
|
}
|
||
|
|
||
|
/* Make physical memory consistent for a set of streaming
|
||
|
* mode DMA translations after a transfer.
|
||
|
*/
|
||
|
void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
|
||
|
{
|
||
|
struct pcidev_cookie *pcp;
|
||
|
struct pci_iommu *iommu;
|
||
|
struct pci_strbuf *strbuf;
|
||
|
unsigned long flags, ctx;
|
||
|
|
||
|
pcp = pdev->sysdata;
|
||
|
iommu = pcp->pbm->iommu;
|
||
|
strbuf = &pcp->pbm->stc;
|
||
|
|
||
|
if (!strbuf->strbuf_enabled)
|
||
|
return;
|
||
|
|
||
|
spin_lock_irqsave(&iommu->lock, flags);
|
||
|
|
||
|
/* Step 1: Record the context, if any. */
|
||
|
ctx = 0;
|
||
|
if (iommu->iommu_ctxflush &&
|
||
|
strbuf->strbuf_ctxflush) {
|
||
|
iopte_t *iopte;
|
||
|
|
||
|
iopte = iommu->page_table +
|
||
|
((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
||
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
||
|
}
|
||
|
|
||
|
/* Step 2: Kick data out of streaming buffers. */
|
||
|
PCI_STC_FLUSHFLAG_INIT(strbuf);
|
||
|
if (iommu->iommu_ctxflush &&
|
||
|
strbuf->strbuf_ctxflush) {
|
||
|
unsigned long matchreg, flushreg;
|
||
|
|
||
|
flushreg = strbuf->strbuf_ctxflush;
|
||
|
matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
|
||
|
do {
|
||
|
pci_iommu_write(flushreg, ctx);
|
||
|
} while (((long)pci_iommu_read(matchreg)) < 0L);
|
||
|
} else {
|
||
|
unsigned long i, npages;
|
||
|
u32 bus_addr;
|
||
|
|
||
|
bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
|
||
|
|
||
|
for(i = 1; i < nelems; i++)
|
||
|
if (!sglist[i].dma_length)
|
||
|
break;
|
||
|
i--;
|
||
|
npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - bus_addr) >> IO_PAGE_SHIFT;
|
||
|
for (i = 0; i < npages; i++, bus_addr += IO_PAGE_SIZE)
|
||
|
pci_iommu_write(strbuf->strbuf_pflush, bus_addr);
|
||
|
}
|
||
|
|
||
|
/* Step 3: Perform flush synchronization sequence. */
|
||
|
pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
|
||
|
(void) pci_iommu_read(iommu->write_complete_reg);
|
||
|
while (!PCI_STC_FLUSHFLAG_SET(strbuf))
|
||
|
membar("#LoadLoad");
|
||
|
|
||
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
||
|
}
|
||
|
|
||
|
static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
|
||
|
{
|
||
|
struct pci_dev *ali_isa_bridge;
|
||
|
u8 val;
|
||
|
|
||
|
/* ALI sound chips generate 31-bits of DMA, a special register
|
||
|
* determines what bit 31 is emitted as.
|
||
|
*/
|
||
|
ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
|
||
|
PCI_DEVICE_ID_AL_M1533,
|
||
|
NULL);
|
||
|
|
||
|
pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
|
||
|
if (set_bit)
|
||
|
val |= 0x01;
|
||
|
else
|
||
|
val &= ~0x01;
|
||
|
pci_write_config_byte(ali_isa_bridge, 0x7e, val);
|
||
|
pci_dev_put(ali_isa_bridge);
|
||
|
}
|
||
|
|
||
|
int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
|
||
|
{
|
||
|
struct pcidev_cookie *pcp = pdev->sysdata;
|
||
|
u64 dma_addr_mask;
|
||
|
|
||
|
if (pdev == NULL) {
|
||
|
dma_addr_mask = 0xffffffff;
|
||
|
} else {
|
||
|
struct pci_iommu *iommu = pcp->pbm->iommu;
|
||
|
|
||
|
dma_addr_mask = iommu->dma_addr_mask;
|
||
|
|
||
|
if (pdev->vendor == PCI_VENDOR_ID_AL &&
|
||
|
pdev->device == PCI_DEVICE_ID_AL_M5451 &&
|
||
|
device_mask == 0x7fffffff) {
|
||
|
ali_sound_dma_hack(pdev,
|
||
|
(dma_addr_mask & 0x80000000) != 0);
|
||
|
return 1;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (device_mask >= (1UL << 32UL))
|
||
|
return 0;
|
||
|
|
||
|
return (device_mask & dma_addr_mask) == dma_addr_mask;
|
||
|
}
|