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68 lines
2.6 KiB
C
68 lines
2.6 KiB
C
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/*
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* Machine check exception header file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2013 IBM Corporation
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* Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
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*/
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#ifndef __ASM_PPC64_MCE_H__
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#define __ASM_PPC64_MCE_H__
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#include <linux/bitops.h>
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/*
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* Machine Check bits on power7 and power8
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*/
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#define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */
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/* SRR1 bits for machine check (On Power7 and Power8) */
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#define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45))
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#define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */
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#define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45))
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/* SRR1 bits for machine check (On Power8) */
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#define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45))
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/* DSISR bits for machine check (On Power7 and Power8) */
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#define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */
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#define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */
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#define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */
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#define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */
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#define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */
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#define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */
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#define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57)) /* P8 too */
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/*
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* DSISR bits for machine check (Power8) in addition to above.
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* Secondary DERAT Multihit
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*/
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#define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54))
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/* SLB error bits */
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#define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \
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P7_DSISR_MC_SLB_PARITY_MFSLB | \
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P7_DSISR_MC_SLB_MULTIHIT | \
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P7_DSISR_MC_SLB_MULTIHIT_PARITY)
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#endif /* __ASM_PPC64_MCE_H__ */
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