2005-04-16 22:20:36 +00:00
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/****************************************************************************/
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/*
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* m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
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*
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* (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
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*/
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/****************************************************************************/
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#ifndef m527xsim_h
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#define m527xsim_h
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/****************************************************************************/
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/*
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* Define the 5270/5271 SIM register set addresses.
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*/
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#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_IRLR 0x18 /* */
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#define MCFINTC_IACKL 0x19 /* */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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#define MCFINT_VECBASE 64 /* Vector base number */
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#define MCFINT_UART0 13 /* Interrupt number for UART0 */
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#define MCFINT_UART1 14 /* Interrupt number for UART1 */
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#define MCFINT_UART2 15 /* Interrupt number for UART2 */
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#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
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/*
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* SDRAM configuration registers.
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*/
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2005-09-12 01:18:10 +00:00
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#ifdef CONFIG_M5271
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2005-04-16 22:20:36 +00:00
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#define MCFSIM_DCR 0x40 /* SDRAM control */
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#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
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#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
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#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
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#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
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2005-09-12 01:18:10 +00:00
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#endif
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#ifdef CONFIG_M5275
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2005-04-16 22:20:36 +00:00
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#define MCFSIM_DMR 0x40 /* SDRAM mode */
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#define MCFSIM_DCR 0x44 /* SDRAM control */
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#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */
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#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */
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#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */
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#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */
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#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */
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#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
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#endif
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2009-06-20 01:11:06 +00:00
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#ifdef CONFIG_M5271
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#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
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#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
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#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
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#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
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#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
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#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
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#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
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#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
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#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
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#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
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#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
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#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
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#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
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#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
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#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
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#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
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#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
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#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
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#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
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#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
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#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
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#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
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#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
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#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
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#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
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#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
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#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
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#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
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#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
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#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
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#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
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#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
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#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
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#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
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#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
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#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
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#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
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#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
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#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
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#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
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#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
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#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
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#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
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#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
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#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
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#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
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#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
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#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
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#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
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#define MCFGPIO_PIN_MAX 100
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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#endif
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#ifdef CONFIG_M5275
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#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004)
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#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005)
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#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008)
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#define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A)
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#define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B)
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#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C)
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#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D)
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#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E)
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#define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F)
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#define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010)
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#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011)
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#define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012)
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#define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013)
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#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014)
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#define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015)
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#define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016)
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#define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017)
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#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018)
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#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020)
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#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021)
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#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024)
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#define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026)
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#define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027)
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#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028)
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#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029)
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#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A)
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#define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B)
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#define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C)
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#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D)
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#define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E)
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#define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F)
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#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030)
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#define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031)
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#define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032)
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#define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033)
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#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034)
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#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C)
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#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D)
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#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040)
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#define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042)
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#define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043)
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#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044)
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#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045)
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#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046)
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#define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047)
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#define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048)
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#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049)
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#define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A)
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#define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B)
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#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C)
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#define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D)
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#define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E)
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#define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F)
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#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050)
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#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058)
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#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059)
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#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C)
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#define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E)
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#define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F)
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#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060)
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#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061)
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#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062)
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#define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063)
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#define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064)
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#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065)
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#define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066)
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#define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067)
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#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068)
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#define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069)
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#define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A)
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#define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B)
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#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C)
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
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#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
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#define MCFGPIO_PIN_MAX 148
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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#endif
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/*
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* EPort
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*/
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#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
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#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
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#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
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2005-09-12 01:18:10 +00:00
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/*
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* GPIO pins setups to enable the UARTs.
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*/
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#ifdef CONFIG_M5271
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#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */
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#define UART0_ENABLE_MASK 0x000f
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#define UART1_ENABLE_MASK 0x0ff0
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#define UART2_ENABLE_MASK 0x3000
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#endif
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#ifdef CONFIG_M5275
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#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */
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#define UART0_ENABLE_MASK 0x000f
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#define UART1_ENABLE_MASK 0x00f0
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#define UART2_ENABLE_MASK 0x3f00
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#endif
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2009-04-30 13:06:45 +00:00
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/*
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* Reset Controll Unit (relative to IPSBAR).
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*/
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#define MCF_RCR 0x110000
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#define MCF_RSR 0x110001
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#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
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#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
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2005-04-16 22:20:36 +00:00
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/****************************************************************************/
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#endif /* m527xsim_h */
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