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350 lines
6.8 KiB
C
350 lines
6.8 KiB
C
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/*
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* Disk Array driver for Compaq SMART2 Controllers
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* Copyright 1998 Compaq Computer Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Questions/Comments/Bugfixes to iss_storagedev@hp.com
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*
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*/
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#ifndef ARRAYCMD_H
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#define ARRAYCMD_H
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#include <asm/types.h>
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#if 0
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#include <linux/blkdev.h>
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#endif
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/* for the Smart Array 42XX cards */
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#define S42XX_REQUEST_PORT_OFFSET 0x40
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#define S42XX_REPLY_INTR_MASK_OFFSET 0x34
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#define S42XX_REPLY_PORT_OFFSET 0x44
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#define S42XX_INTR_STATUS 0x30
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#define S42XX_INTR_OFF 0x08
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#define S42XX_INTR_PENDING 0x08
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#define COMMAND_FIFO 0x04
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#define COMMAND_COMPLETE_FIFO 0x08
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#define INTR_MASK 0x0C
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#define INTR_STATUS 0x10
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#define INTR_PENDING 0x14
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#define FIFO_NOT_EMPTY 0x01
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#define FIFO_NOT_FULL 0x02
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#define BIG_PROBLEM 0x40
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#define LOG_NOT_CONF 2
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#pragma pack(1)
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typedef struct {
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__u32 size;
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__u32 addr;
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} sg_t;
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#define RCODE_NONFATAL 0x02
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#define RCODE_FATAL 0x04
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#define RCODE_INVREQ 0x10
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typedef struct {
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__u16 next;
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__u8 cmd;
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__u8 rcode;
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__u32 blk;
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__u16 blk_cnt;
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__u8 sg_cnt;
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__u8 reserved;
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} rhdr_t;
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#define SG_MAX 32
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typedef struct {
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rhdr_t hdr;
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sg_t sg[SG_MAX];
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__u32 bp;
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} rblk_t;
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typedef struct {
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__u8 unit;
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__u8 prio;
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__u16 size;
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} chdr_t;
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#define CMD_RWREQ 0x00
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#define CMD_IOCTL_PEND 0x01
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#define CMD_IOCTL_DONE 0x02
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typedef struct cmdlist {
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chdr_t hdr;
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rblk_t req;
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__u32 size;
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int retry_cnt;
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__u32 busaddr;
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int ctlr;
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struct cmdlist *prev;
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struct cmdlist *next;
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struct request *rq;
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int type;
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} cmdlist_t;
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#define ID_CTLR 0x11
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typedef struct {
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__u8 nr_drvs;
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__u32 cfg_sig;
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__u8 firm_rev[4];
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__u8 rom_rev[4];
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__u8 hw_rev;
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__u32 bb_rev;
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__u32 drv_present_map;
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__u32 ext_drv_map;
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__u32 board_id;
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__u8 cfg_error;
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__u32 non_disk_bits;
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__u8 bad_ram_addr;
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__u8 cpu_rev;
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__u8 pdpi_rev;
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__u8 epic_rev;
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__u8 wcxc_rev;
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__u8 marketing_rev;
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__u8 ctlr_flags;
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__u8 host_flags;
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__u8 expand_dis;
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__u8 scsi_chips;
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__u32 max_req_blocks;
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__u32 ctlr_clock;
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__u8 drvs_per_bus;
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__u16 big_drv_present_map[8];
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__u16 big_ext_drv_map[8];
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__u16 big_non_disk_map[8];
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__u16 task_flags;
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__u8 icl_bus;
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__u8 red_modes;
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__u8 cur_red_mode;
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__u8 red_ctlr_stat;
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__u8 red_fail_reason;
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__u8 reserved[403];
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} id_ctlr_t;
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typedef struct {
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__u16 cyl;
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__u8 heads;
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__u8 xsig;
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__u8 psectors;
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__u16 wpre;
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__u8 maxecc;
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__u8 drv_ctrl;
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__u16 pcyls;
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__u8 pheads;
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__u16 landz;
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__u8 sect_per_track;
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__u8 cksum;
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} drv_param_t;
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#define ID_LOG_DRV 0x10
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typedef struct {
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__u16 blk_size;
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__u32 nr_blks;
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drv_param_t drv;
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__u8 fault_tol;
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__u8 reserved;
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__u8 bios_disable;
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} id_log_drv_t;
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#define ID_LOG_DRV_EXT 0x18
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typedef struct {
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__u32 log_drv_id;
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__u8 log_drv_label[64];
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__u8 reserved[418];
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} id_log_drv_ext_t;
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#define SENSE_LOG_DRV_STAT 0x12
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typedef struct {
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__u8 status;
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__u32 fail_map;
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__u16 read_err[32];
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__u16 write_err[32];
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__u8 drv_err_data[256];
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__u8 drq_timeout[32];
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__u32 blks_to_recover;
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__u8 drv_recovering;
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__u16 remap_cnt[32];
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__u32 replace_drv_map;
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__u32 act_spare_map;
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__u8 spare_stat;
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__u8 spare_repl_map[32];
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__u32 repl_ok_map;
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__u8 media_exch;
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__u8 cache_fail;
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__u8 expn_fail;
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__u8 unit_flags;
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__u16 big_fail_map[8];
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__u16 big_remap_map[128];
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__u16 big_repl_map[8];
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__u16 big_act_spare_map[8];
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__u8 big_spar_repl_map[128];
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__u16 big_repl_ok_map[8];
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__u8 big_drv_rebuild;
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__u8 reserved[36];
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} sense_log_drv_stat_t;
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#define START_RECOVER 0x13
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#define ID_PHYS_DRV 0x15
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typedef struct {
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__u8 scsi_bus;
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__u8 scsi_id;
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__u16 blk_size;
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__u32 nr_blks;
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__u32 rsvd_blks;
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__u8 drv_model[40];
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__u8 drv_sn[40];
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__u8 drv_fw[8];
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__u8 scsi_iq_bits;
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__u8 compaq_drv_stmp;
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__u8 last_fail;
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__u8 phys_drv_flags;
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__u8 phys_drv_flags1;
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__u8 scsi_lun;
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__u8 phys_drv_flags2;
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__u8 reserved;
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__u32 spi_speed_rules;
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__u8 phys_connector[2];
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__u8 phys_box_on_bus;
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__u8 phys_bay_in_box;
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} id_phys_drv_t;
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#define BLINK_DRV_LEDS 0x16
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typedef struct {
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__u32 blink_duration;
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__u32 reserved;
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__u8 blink[256];
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__u8 reserved1[248];
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} blink_drv_leds_t;
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#define SENSE_BLINK_LEDS 0x17
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typedef struct {
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__u32 blink_duration;
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__u32 btime_elap;
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__u8 blink[256];
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__u8 reserved1[248];
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} sense_blink_leds_t;
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#define IDA_READ 0x20
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#define IDA_WRITE 0x30
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#define IDA_WRITE_MEDIA 0x31
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#define RESET_TO_DIAG 0x40
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#define DIAG_PASS_THRU 0x41
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#define SENSE_CONFIG 0x50
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#define SET_CONFIG 0x51
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typedef struct {
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__u32 cfg_sig;
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__u16 compat_port;
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__u8 data_dist_mode;
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__u8 surf_an_ctrl;
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__u16 ctlr_phys_drv;
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__u16 log_unit_phys_drv;
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__u16 fault_tol_mode;
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__u8 phys_drv_param[16];
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drv_param_t drv;
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__u32 drv_asgn_map;
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__u16 dist_factor;
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__u32 spare_asgn_map;
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__u8 reserved[6];
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__u16 os;
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__u8 ctlr_order;
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__u8 extra_info;
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__u32 data_offs;
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__u8 parity_backedout_write_drvs;
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__u8 parity_dist_mode;
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__u8 parity_shift_fact;
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__u8 bios_disable_flag;
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__u32 blks_on_vol;
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__u32 blks_per_drv;
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__u8 scratch[16];
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__u16 big_drv_map[8];
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__u16 big_spare_map[8];
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__u8 ss_source_vol;
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__u8 mix_drv_cap_range;
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struct {
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__u16 big_drv_map[8];
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__u32 blks_per_drv;
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__u16 fault_tol_mode;
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__u16 dist_factor;
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} MDC_range[4];
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__u8 reserved1[248];
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} config_t;
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#define BYPASS_VOL_STATE 0x52
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#define SS_CREATE_VOL 0x53
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#define CHANGE_CONFIG 0x54
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#define SENSE_ORIG_CONF 0x55
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#define REORDER_LOG_DRV 0x56
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typedef struct {
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__u8 old_units[32];
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} reorder_log_drv_t;
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#define LABEL_LOG_DRV 0x57
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typedef struct {
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__u8 log_drv_label[64];
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} label_log_drv_t;
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#define SS_TO_VOL 0x58
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#define SET_SURF_DELAY 0x60
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typedef struct {
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__u16 delay;
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__u8 reserved[510];
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} surf_delay_t;
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#define SET_OVERHEAT_DELAY 0x61
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typedef struct {
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__u16 delay;
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} overhead_delay_t;
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#define SET_MP_DELAY
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typedef struct {
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__u16 delay;
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__u8 reserved[510];
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} mp_delay_t;
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#define PASSTHRU_A 0x91
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typedef struct {
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__u8 target;
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__u8 bus;
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__u8 lun;
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__u32 timeout;
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__u32 flags;
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__u8 status;
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__u8 error;
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__u8 cdb_len;
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__u8 sense_error;
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__u8 sense_key;
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__u32 sense_info;
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__u8 sense_code;
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__u8 sense_qual;
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__u32 residual;
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__u8 reserved[4];
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__u8 cdb[12];
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} scsi_param_t;
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#define RESUME_BACKGROUND_ACTIVITY 0x99
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#define SENSE_CONTROLLER_PERFORMANCE 0xa8
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#define FLUSH_CACHE 0xc2
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#define COLLECT_BUFFER 0xd2
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#define READ_FLASH_ROM 0xf6
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#define WRITE_FLASH_ROM 0xf7
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#pragma pack()
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#endif /* ARRAYCMD_H */
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