2019-04-02 10:31:55 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2010-10-28 01:43:53 +00:00
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/*
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* AD7150 capacitive sensor driver supporting AD7150/1/6
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*
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2011-09-02 16:25:22 +00:00
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* Copyright 2010-2011 Analog Devices Inc.
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2021-03-14 18:15:09 +00:00
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* Copyright 2021 Jonathan Cameron <Jonathan.Cameron@huawei.com>
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2010-10-28 01:43:53 +00:00
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*/
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2019-05-19 01:04:56 +00:00
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#include <linux/bitfield.h>
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2010-10-28 01:43:53 +00:00
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#include <linux/device.h>
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2021-03-14 18:15:01 +00:00
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#include <linux/interrupt.h>
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2021-03-14 18:14:59 +00:00
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#include <linux/irq.h>
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2021-03-14 18:15:01 +00:00
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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2011-07-03 19:49:50 +00:00
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#include <linux/module.h>
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2021-03-14 18:15:07 +00:00
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#include <linux/mod_devicetable.h>
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2021-03-14 18:15:06 +00:00
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#include <linux/regulator/consumer.h>
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2021-03-14 18:15:01 +00:00
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#include <linux/slab.h>
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2010-10-28 01:43:53 +00:00
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2012-04-25 14:54:58 +00:00
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/events.h>
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2010-10-28 01:43:53 +00:00
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2021-03-14 18:15:00 +00:00
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#define AD7150_STATUS_REG 0
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#define AD7150_STATUS_OUT1 BIT(3)
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#define AD7150_STATUS_OUT2 BIT(5)
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#define AD7150_CH1_DATA_HIGH_REG 1
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#define AD7150_CH2_DATA_HIGH_REG 3
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#define AD7150_CH1_AVG_HIGH_REG 5
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#define AD7150_CH2_AVG_HIGH_REG 7
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#define AD7150_CH1_SENSITIVITY_REG 9
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#define AD7150_CH1_THR_HOLD_H_REG 9
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#define AD7150_CH1_TIMEOUT_REG 10
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#define AD7150_CH_TIMEOUT_RECEDING GENMASK(3, 0)
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#define AD7150_CH_TIMEOUT_APPROACHING GENMASK(7, 4)
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#define AD7150_CH1_SETUP_REG 11
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#define AD7150_CH2_SENSITIVITY_REG 12
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#define AD7150_CH2_THR_HOLD_H_REG 12
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#define AD7150_CH2_TIMEOUT_REG 13
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#define AD7150_CH2_SETUP_REG 14
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#define AD7150_CFG_REG 15
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#define AD7150_CFG_FIX BIT(7)
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#define AD7150_CFG_THRESHTYPE_MSK GENMASK(6, 5)
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#define AD7150_CFG_TT_NEG 0x0
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#define AD7150_CFG_TT_POS 0x1
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#define AD7150_CFG_TT_IN_WINDOW 0x2
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#define AD7150_CFG_TT_OUT_WINDOW 0x3
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#define AD7150_PD_TIMER_REG 16
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#define AD7150_CH1_CAPDAC_REG 17
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#define AD7150_CH2_CAPDAC_REG 18
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#define AD7150_SN3_REG 19
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#define AD7150_SN2_REG 20
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#define AD7150_SN1_REG 21
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#define AD7150_SN0_REG 22
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#define AD7150_ID_REG 23
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2021-03-14 18:14:53 +00:00
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enum {
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AD7150,
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AD7151,
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};
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2011-09-02 16:25:20 +00:00
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/**
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* struct ad7150_chip_info - instance specific chip data
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* @client: i2c client for this device
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* @threshold: thresholds for simple capacitance value events
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* @thresh_sensitivity: threshold for simple capacitance offset
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* from 'average' value.
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* @thresh_timeout: a timeout, in samples from the moment an
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* adaptive threshold event occurs to when the average
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2021-03-14 18:14:51 +00:00
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* value jumps to current value. Note made up of two fields,
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* 3:0 are for timeout receding - applies if below lower threshold
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* 7:4 are for timeout approaching - applies if above upper threshold
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2011-09-02 16:25:20 +00:00
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* @state_lock: ensure consistent state of this structure wrt the
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* hardware.
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2021-03-14 18:14:59 +00:00
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* @interrupts: one or two interrupt numbers depending on device type.
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* @int_enabled: is a given interrupt currently enabled.
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* @type: threshold type
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* @dir: threshold direction
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2011-09-02 16:25:20 +00:00
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*/
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2010-10-28 01:43:53 +00:00
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struct ad7150_chip_info {
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struct i2c_client *client;
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2011-09-02 16:25:20 +00:00
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u16 threshold[2][2];
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u8 thresh_sensitivity[2][2];
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u8 thresh_timeout[2][2];
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struct mutex state_lock;
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2021-03-14 18:14:59 +00:00
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int interrupts[2];
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bool int_enabled[2];
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enum iio_event_type type;
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enum iio_event_direction dir;
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2010-10-28 01:43:53 +00:00
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};
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2011-09-02 16:25:20 +00:00
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static const u8 ad7150_addresses[][6] = {
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2021-03-14 18:15:00 +00:00
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{ AD7150_CH1_DATA_HIGH_REG, AD7150_CH1_AVG_HIGH_REG,
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AD7150_CH1_SETUP_REG, AD7150_CH1_THR_HOLD_H_REG,
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AD7150_CH1_SENSITIVITY_REG, AD7150_CH1_TIMEOUT_REG },
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{ AD7150_CH2_DATA_HIGH_REG, AD7150_CH2_AVG_HIGH_REG,
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AD7150_CH2_SETUP_REG, AD7150_CH2_THR_HOLD_H_REG,
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AD7150_CH2_SENSITIVITY_REG, AD7150_CH2_TIMEOUT_REG },
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2011-09-02 16:25:20 +00:00
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};
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2010-10-28 01:43:53 +00:00
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2011-09-02 16:25:20 +00:00
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static int ad7150_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long mask)
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2010-10-28 01:43:53 +00:00
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{
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2011-09-02 16:25:20 +00:00
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struct ad7150_chip_info *chip = iio_priv(indio_dev);
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2018-10-05 08:04:44 +00:00
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int channel = chan->channel;
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2021-03-14 18:15:02 +00:00
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int ret;
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2010-10-28 01:43:53 +00:00
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2011-09-02 16:25:20 +00:00
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switch (mask) {
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2012-04-15 16:41:26 +00:00
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case IIO_CHAN_INFO_RAW:
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2021-03-14 18:14:48 +00:00
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ret = i2c_smbus_read_word_swapped(chip->client,
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ad7150_addresses[channel][0]);
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2011-09-02 16:25:20 +00:00
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if (ret < 0)
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return ret;
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2021-03-14 18:15:04 +00:00
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*val = ret >> 4;
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2021-03-14 18:14:48 +00:00
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2011-09-02 16:25:20 +00:00
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return IIO_VAL_INT;
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2011-10-26 16:41:36 +00:00
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case IIO_CHAN_INFO_AVERAGE_RAW:
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2021-03-14 18:14:48 +00:00
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ret = i2c_smbus_read_word_swapped(chip->client,
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ad7150_addresses[channel][1]);
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2011-09-02 16:25:20 +00:00
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if (ret < 0)
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return ret;
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2021-03-14 18:14:48 +00:00
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*val = ret;
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2021-03-14 18:15:05 +00:00
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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/*
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* Base units for capacitance are nano farads and the value
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* calculated from the datasheet formula is in picofarad
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* so multiply by 1000
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*/
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*val = 1000;
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*val2 = 40944 >> 4; /* To match shift in _RAW */
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return IIO_VAL_FRACTIONAL;
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case IIO_CHAN_INFO_OFFSET:
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*val = -(12288 >> 4); /* To match shift in _RAW */
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2021-03-14 18:14:56 +00:00
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SAMP_FREQ:
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/* Strangely same for both 1 and 2 chan parts */
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*val = 100;
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2011-09-02 16:25:20 +00:00
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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2010-10-28 01:43:53 +00:00
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}
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}
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2013-10-07 14:11:00 +00:00
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static int ad7150_read_event_config(struct iio_dev *indio_dev,
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2018-03-08 23:56:07 +00:00
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir)
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2010-10-28 01:43:53 +00:00
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{
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2021-03-14 18:15:02 +00:00
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struct ad7150_chip_info *chip = iio_priv(indio_dev);
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2011-09-02 16:25:20 +00:00
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u8 threshtype;
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2019-05-19 01:04:56 +00:00
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bool thrfixed;
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2021-03-14 18:15:02 +00:00
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int ret;
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2010-10-28 01:43:53 +00:00
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2021-03-14 18:15:00 +00:00
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ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);
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2011-09-02 16:25:20 +00:00
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if (ret < 0)
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return ret;
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2010-10-28 01:43:53 +00:00
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2021-03-14 18:15:00 +00:00
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threshtype = FIELD_GET(AD7150_CFG_THRESHTYPE_MSK, ret);
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2019-05-19 01:04:56 +00:00
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/*check if threshold mode is fixed or adaptive*/
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thrfixed = FIELD_GET(AD7150_CFG_FIX, ret);
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2011-09-02 16:25:20 +00:00
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2013-10-07 14:11:00 +00:00
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switch (type) {
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2011-09-02 16:25:20 +00:00
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case IIO_EV_TYPE_THRESH_ADAPTIVE:
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2013-10-07 14:11:00 +00:00
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if (dir == IIO_EV_DIR_RISING)
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2021-03-14 18:15:00 +00:00
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return !thrfixed && (threshtype == AD7150_CFG_TT_POS);
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return !thrfixed && (threshtype == AD7150_CFG_TT_NEG);
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2011-09-02 16:25:20 +00:00
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case IIO_EV_TYPE_THRESH:
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2013-10-07 14:11:00 +00:00
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if (dir == IIO_EV_DIR_RISING)
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2021-03-14 18:15:00 +00:00
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return thrfixed && (threshtype == AD7150_CFG_TT_POS);
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return thrfixed && (threshtype == AD7150_CFG_TT_NEG);
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2013-10-07 14:11:00 +00:00
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default:
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break;
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2012-09-28 09:57:00 +00:00
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}
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2010-10-28 01:43:53 +00:00
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return -EINVAL;
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}
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2021-03-14 18:15:03 +00:00
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/* state_lock should be held to ensure consistent state */
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2013-10-07 14:11:00 +00:00
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static int ad7150_write_event_params(struct iio_dev *indio_dev,
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2015-12-29 11:27:31 +00:00
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unsigned int chan,
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enum iio_event_type type,
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enum iio_event_direction dir)
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2010-10-28 01:43:53 +00:00
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{
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2011-09-02 16:25:20 +00:00
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struct ad7150_chip_info *chip = iio_priv(indio_dev);
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2013-10-07 14:11:00 +00:00
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int rising = (dir == IIO_EV_DIR_RISING);
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2021-03-14 18:14:59 +00:00
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/* Only update value live, if parameter is in use */
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if ((type != chip->type) || (dir != chip->dir))
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2011-09-02 16:25:20 +00:00
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return 0;
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2013-10-07 14:11:00 +00:00
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switch (type) {
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2011-09-02 16:25:20 +00:00
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/* Note completely different from the adaptive versions */
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2021-03-14 18:14:50 +00:00
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case IIO_EV_TYPE_THRESH: {
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u16 value = chip->threshold[rising][chan];
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2021-03-14 18:14:48 +00:00
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return i2c_smbus_write_word_swapped(chip->client,
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ad7150_addresses[chan][3],
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value);
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2021-03-14 18:14:50 +00:00
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}
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case IIO_EV_TYPE_THRESH_ADAPTIVE: {
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int ret;
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u8 sens, timeout;
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2011-09-02 16:25:20 +00:00
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sens = chip->thresh_sensitivity[rising][chan];
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2021-03-14 18:14:50 +00:00
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ret = i2c_smbus_write_byte_data(chip->client,
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ad7150_addresses[chan][4],
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sens);
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if (ret)
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return ret;
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2021-03-14 18:14:51 +00:00
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/*
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* Single timeout register contains timeouts for both
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* directions.
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*/
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timeout = FIELD_PREP(AD7150_CH_TIMEOUT_APPROACHING,
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chip->thresh_timeout[1][chan]);
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timeout |= FIELD_PREP(AD7150_CH_TIMEOUT_RECEDING,
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chip->thresh_timeout[0][chan]);
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2021-03-14 18:14:50 +00:00
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return i2c_smbus_write_byte_data(chip->client,
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ad7150_addresses[chan][5],
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timeout);
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}
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2011-09-02 16:25:20 +00:00
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default:
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return -EINVAL;
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2012-09-28 09:57:00 +00:00
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}
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2010-10-28 01:43:53 +00:00
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}
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2011-09-02 16:25:20 +00:00
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static int ad7150_write_event_config(struct iio_dev *indio_dev,
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2015-12-29 11:27:31 +00:00
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir, int state)
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2010-10-28 01:43:53 +00:00
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{
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2011-09-02 16:25:20 +00:00
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struct ad7150_chip_info *chip = iio_priv(indio_dev);
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2021-04-06 08:23:37 +00:00
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int ret = 0;
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2010-10-28 01:43:53 +00:00
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2021-03-14 18:14:59 +00:00
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/*
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* There is only a single shared control and no on chip
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* interrupt disables for the two interrupt lines.
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* So, enabling will switch the events configured to enable
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* whatever was most recently requested and if necessary enable_irq()
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* the interrupt and any disable will disable_irq() for that
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* channels interrupt.
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*/
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if (!state) {
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if ((chip->int_enabled[chan->channel]) &&
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(type == chip->type) && (dir == chip->dir)) {
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disable_irq(chip->interrupts[chan->channel]);
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chip->int_enabled[chan->channel] = false;
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}
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2011-09-02 16:25:20 +00:00
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return 0;
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2021-03-14 18:14:59 +00:00
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}
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2011-09-02 16:25:20 +00:00
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mutex_lock(&chip->state_lock);
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2021-03-14 18:14:59 +00:00
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if ((type != chip->type) || (dir != chip->dir)) {
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2021-03-14 18:15:02 +00:00
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int rising = (dir == IIO_EV_DIR_RISING);
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u8 thresh_type, cfg, fixed;
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2010-10-28 01:43:53 +00:00
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2021-03-14 18:14:59 +00:00
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/*
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* Need to temporarily disable both interrupts if
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* enabled - this is to avoid races around changing
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* config and thresholds.
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* Note enable/disable_irq() are reference counted so
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* no need to check if already enabled.
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*/
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disable_irq(chip->interrupts[0]);
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disable_irq(chip->interrupts[1]);
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2011-09-02 16:25:20 +00:00
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|
|
2021-03-14 18:15:00 +00:00
|
|
|
ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);
|
2021-03-14 18:14:59 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error_ret;
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2021-03-14 18:15:00 +00:00
|
|
|
cfg = ret & ~(AD7150_CFG_THRESHTYPE_MSK | AD7150_CFG_FIX);
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2021-03-14 18:15:00 +00:00
|
|
|
if (type == IIO_EV_TYPE_THRESH_ADAPTIVE)
|
|
|
|
fixed = 0;
|
|
|
|
else
|
|
|
|
fixed = 1;
|
|
|
|
|
|
|
|
if (rising)
|
|
|
|
thresh_type = AD7150_CFG_TT_POS;
|
|
|
|
else
|
|
|
|
thresh_type = AD7150_CFG_TT_NEG;
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2021-03-14 18:15:00 +00:00
|
|
|
cfg |= FIELD_PREP(AD7150_CFG_FIX, fixed) |
|
|
|
|
FIELD_PREP(AD7150_CFG_THRESHTYPE_MSK, thresh_type);
|
2021-03-14 18:14:59 +00:00
|
|
|
|
2021-03-14 18:15:00 +00:00
|
|
|
ret = i2c_smbus_write_byte_data(chip->client, AD7150_CFG_REG,
|
|
|
|
cfg);
|
2021-03-14 18:14:59 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto error_ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* There is a potential race condition here, but not easy
|
|
|
|
* to close given we can't disable the interrupt at the
|
|
|
|
* chip side of things. Rely on the status bit.
|
|
|
|
*/
|
|
|
|
chip->type = type;
|
|
|
|
chip->dir = dir;
|
|
|
|
|
|
|
|
/* update control attributes */
|
|
|
|
ret = ad7150_write_event_params(indio_dev, chan->channel, type,
|
|
|
|
dir);
|
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
/* reenable any irq's we disabled whilst changing mode */
|
|
|
|
enable_irq(chip->interrupts[0]);
|
|
|
|
enable_irq(chip->interrupts[1]);
|
|
|
|
}
|
|
|
|
if (!chip->int_enabled[chan->channel]) {
|
|
|
|
enable_irq(chip->interrupts[chan->channel]);
|
|
|
|
chip->int_enabled[chan->channel] = true;
|
|
|
|
}
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2011-09-02 16:25:20 +00:00
|
|
|
error_ret:
|
|
|
|
mutex_unlock(&chip->state_lock);
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2016-12-03 13:44:30 +00:00
|
|
|
return ret;
|
2010-10-28 01:43:53 +00:00
|
|
|
}
|
|
|
|
|
2011-09-02 16:25:20 +00:00
|
|
|
static int ad7150_read_event_value(struct iio_dev *indio_dev,
|
2013-10-07 14:11:00 +00:00
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir,
|
|
|
|
enum iio_event_info info,
|
|
|
|
int *val, int *val2)
|
2010-10-28 01:43:53 +00:00
|
|
|
{
|
2011-09-02 16:25:20 +00:00
|
|
|
struct ad7150_chip_info *chip = iio_priv(indio_dev);
|
2013-10-07 14:11:00 +00:00
|
|
|
int rising = (dir == IIO_EV_DIR_RISING);
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2011-09-02 16:25:20 +00:00
|
|
|
/* Complex register sharing going on here */
|
2021-03-14 18:14:58 +00:00
|
|
|
switch (info) {
|
|
|
|
case IIO_EV_INFO_VALUE:
|
|
|
|
switch (type) {
|
|
|
|
case IIO_EV_TYPE_THRESH_ADAPTIVE:
|
|
|
|
*val = chip->thresh_sensitivity[rising][chan->channel];
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
case IIO_EV_TYPE_THRESH:
|
|
|
|
*val = chip->threshold[rising][chan->channel];
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
case IIO_EV_INFO_TIMEOUT:
|
|
|
|
*val = 0;
|
|
|
|
*val2 = chip->thresh_timeout[rising][chan->channel] * 10000;
|
|
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
2011-09-02 16:25:20 +00:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
2013-10-10 23:07:59 +00:00
|
|
|
}
|
2010-10-28 01:43:53 +00:00
|
|
|
}
|
|
|
|
|
2011-09-02 16:25:20 +00:00
|
|
|
static int ad7150_write_event_value(struct iio_dev *indio_dev,
|
2015-12-29 11:27:31 +00:00
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir,
|
|
|
|
enum iio_event_info info,
|
|
|
|
int val, int val2)
|
2010-10-28 01:43:53 +00:00
|
|
|
{
|
|
|
|
int ret;
|
2011-09-02 16:25:20 +00:00
|
|
|
struct ad7150_chip_info *chip = iio_priv(indio_dev);
|
2013-10-07 14:11:00 +00:00
|
|
|
int rising = (dir == IIO_EV_DIR_RISING);
|
2011-09-02 16:25:20 +00:00
|
|
|
|
|
|
|
mutex_lock(&chip->state_lock);
|
2021-03-14 18:14:58 +00:00
|
|
|
switch (info) {
|
|
|
|
case IIO_EV_INFO_VALUE:
|
|
|
|
switch (type) {
|
|
|
|
case IIO_EV_TYPE_THRESH_ADAPTIVE:
|
|
|
|
chip->thresh_sensitivity[rising][chan->channel] = val;
|
|
|
|
break;
|
|
|
|
case IIO_EV_TYPE_THRESH:
|
|
|
|
chip->threshold[rising][chan->channel] = val;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_ret;
|
|
|
|
}
|
2011-09-02 16:25:20 +00:00
|
|
|
break;
|
2021-03-14 18:14:58 +00:00
|
|
|
case IIO_EV_INFO_TIMEOUT: {
|
|
|
|
/*
|
|
|
|
* Raw timeout is in cycles of 10 msecs as long as both
|
|
|
|
* channels are enabled.
|
|
|
|
* In terms of INT_PLUS_MICRO, that is in units of 10,000
|
|
|
|
*/
|
|
|
|
int timeout = val2 / 10000;
|
|
|
|
|
|
|
|
if (val != 0 || timeout < 0 || timeout > 15 || val2 % 10000) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
chip->thresh_timeout[rising][chan->channel] = timeout;
|
2011-09-02 16:25:20 +00:00
|
|
|
break;
|
2021-03-14 18:14:58 +00:00
|
|
|
}
|
2011-09-02 16:25:20 +00:00
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_ret;
|
2012-09-28 09:57:00 +00:00
|
|
|
}
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2011-09-02 16:25:20 +00:00
|
|
|
/* write back if active */
|
2013-10-07 14:11:00 +00:00
|
|
|
ret = ad7150_write_event_params(indio_dev, chan->channel, type, dir);
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2011-09-02 16:25:20 +00:00
|
|
|
error_ret:
|
2011-10-06 06:17:00 +00:00
|
|
|
mutex_unlock(&chip->state_lock);
|
2011-09-02 16:25:20 +00:00
|
|
|
return ret;
|
2010-10-28 01:43:53 +00:00
|
|
|
}
|
|
|
|
|
2013-10-07 14:11:00 +00:00
|
|
|
static const struct iio_event_spec ad7150_events[] = {
|
|
|
|
{
|
|
|
|
.type = IIO_EV_TYPE_THRESH,
|
|
|
|
.dir = IIO_EV_DIR_RISING,
|
|
|
|
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
|
|
|
|
BIT(IIO_EV_INFO_ENABLE),
|
|
|
|
}, {
|
|
|
|
.type = IIO_EV_TYPE_THRESH,
|
|
|
|
.dir = IIO_EV_DIR_FALLING,
|
|
|
|
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
|
|
|
|
BIT(IIO_EV_INFO_ENABLE),
|
|
|
|
}, {
|
|
|
|
.type = IIO_EV_TYPE_THRESH_ADAPTIVE,
|
|
|
|
.dir = IIO_EV_DIR_RISING,
|
|
|
|
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
|
2021-03-14 18:14:58 +00:00
|
|
|
BIT(IIO_EV_INFO_ENABLE) |
|
|
|
|
BIT(IIO_EV_INFO_TIMEOUT),
|
2013-10-07 14:11:00 +00:00
|
|
|
}, {
|
|
|
|
.type = IIO_EV_TYPE_THRESH_ADAPTIVE,
|
|
|
|
.dir = IIO_EV_DIR_FALLING,
|
|
|
|
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
|
2021-03-14 18:14:58 +00:00
|
|
|
BIT(IIO_EV_INFO_ENABLE) |
|
|
|
|
BIT(IIO_EV_INFO_TIMEOUT),
|
2013-10-07 14:11:00 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2019-05-18 22:41:36 +00:00
|
|
|
#define AD7150_CAPACITANCE_CHAN(_chan) { \
|
|
|
|
.type = IIO_CAPACITANCE, \
|
|
|
|
.indexed = 1, \
|
|
|
|
.channel = _chan, \
|
|
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
|
|
|
|
BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
|
2021-03-14 18:15:05 +00:00
|
|
|
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
|
|
|
|
BIT(IIO_CHAN_INFO_OFFSET), \
|
2021-03-14 18:14:56 +00:00
|
|
|
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
|
2019-05-18 22:41:36 +00:00
|
|
|
.event_spec = ad7150_events, \
|
|
|
|
.num_event_specs = ARRAY_SIZE(ad7150_events), \
|
|
|
|
}
|
|
|
|
|
2021-03-14 18:14:53 +00:00
|
|
|
#define AD7150_CAPACITANCE_CHAN_NO_IRQ(_chan) { \
|
|
|
|
.type = IIO_CAPACITANCE, \
|
|
|
|
.indexed = 1, \
|
|
|
|
.channel = _chan, \
|
|
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
|
|
|
|
BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
|
2021-03-14 18:15:05 +00:00
|
|
|
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
|
|
|
|
BIT(IIO_CHAN_INFO_OFFSET), \
|
2021-03-14 18:14:56 +00:00
|
|
|
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
|
2021-03-14 18:14:53 +00:00
|
|
|
}
|
|
|
|
|
2011-09-02 16:25:20 +00:00
|
|
|
static const struct iio_chan_spec ad7150_channels[] = {
|
2019-05-18 22:41:36 +00:00
|
|
|
AD7150_CAPACITANCE_CHAN(0),
|
2021-03-14 18:14:53 +00:00
|
|
|
AD7150_CAPACITANCE_CHAN(1),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct iio_chan_spec ad7150_channels_no_irq[] = {
|
|
|
|
AD7150_CAPACITANCE_CHAN_NO_IRQ(0),
|
|
|
|
AD7150_CAPACITANCE_CHAN_NO_IRQ(1),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct iio_chan_spec ad7151_channels[] = {
|
|
|
|
AD7150_CAPACITANCE_CHAN(0),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct iio_chan_spec ad7151_channels_no_irq[] = {
|
|
|
|
AD7150_CAPACITANCE_CHAN_NO_IRQ(0),
|
2011-09-02 16:25:20 +00:00
|
|
|
};
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2021-03-14 18:14:59 +00:00
|
|
|
static irqreturn_t __ad7150_event_handler(void *private, u8 status_mask,
|
|
|
|
int channel)
|
2010-10-28 01:43:53 +00:00
|
|
|
{
|
2011-05-18 13:41:08 +00:00
|
|
|
struct iio_dev *indio_dev = private;
|
2011-06-27 12:07:21 +00:00
|
|
|
struct ad7150_chip_info *chip = iio_priv(indio_dev);
|
2016-03-09 18:05:49 +00:00
|
|
|
s64 timestamp = iio_get_time_ns(indio_dev);
|
2021-03-14 18:14:59 +00:00
|
|
|
int int_status;
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2021-03-14 18:15:00 +00:00
|
|
|
int_status = i2c_smbus_read_byte_data(chip->client, AD7150_STATUS_REG);
|
2021-03-14 18:14:59 +00:00
|
|
|
if (int_status < 0)
|
2011-09-02 16:25:20 +00:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
2021-03-14 18:14:59 +00:00
|
|
|
if (!(int_status & status_mask))
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
|
|
|
iio_push_event(indio_dev,
|
|
|
|
IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, channel,
|
|
|
|
chip->type, chip->dir),
|
|
|
|
timestamp);
|
2011-09-02 16:25:20 +00:00
|
|
|
|
2011-05-18 13:41:08 +00:00
|
|
|
return IRQ_HANDLED;
|
2010-10-28 01:43:53 +00:00
|
|
|
}
|
|
|
|
|
2021-03-14 18:14:59 +00:00
|
|
|
static irqreturn_t ad7150_event_handler_ch1(int irq, void *private)
|
|
|
|
{
|
|
|
|
return __ad7150_event_handler(private, AD7150_STATUS_OUT1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t ad7150_event_handler_ch2(int irq, void *private)
|
|
|
|
{
|
|
|
|
return __ad7150_event_handler(private, AD7150_STATUS_OUT2, 1);
|
|
|
|
}
|
|
|
|
|
2021-03-14 18:14:58 +00:00
|
|
|
static IIO_CONST_ATTR(in_capacitance_thresh_adaptive_timeout_available,
|
|
|
|
"[0 0.01 0.15]");
|
|
|
|
|
2010-10-28 01:43:53 +00:00
|
|
|
static struct attribute *ad7150_event_attributes[] = {
|
2021-03-14 18:14:58 +00:00
|
|
|
&iio_const_attr_in_capacitance_thresh_adaptive_timeout_available
|
2011-09-02 16:25:20 +00:00
|
|
|
.dev_attr.attr,
|
2010-10-28 01:43:53 +00:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
2016-10-01 19:15:15 +00:00
|
|
|
static const struct attribute_group ad7150_event_attribute_group = {
|
2010-10-28 01:43:53 +00:00
|
|
|
.attrs = ad7150_event_attributes,
|
2011-08-30 11:32:45 +00:00
|
|
|
.name = "events",
|
2010-10-28 01:43:53 +00:00
|
|
|
};
|
|
|
|
|
2011-05-18 13:42:37 +00:00
|
|
|
static const struct iio_info ad7150_info = {
|
|
|
|
.event_attrs = &ad7150_event_attribute_group,
|
2011-09-02 16:25:20 +00:00
|
|
|
.read_raw = &ad7150_read_raw,
|
2013-12-07 10:45:00 +00:00
|
|
|
.read_event_config = &ad7150_read_event_config,
|
|
|
|
.write_event_config = &ad7150_write_event_config,
|
|
|
|
.read_event_value = &ad7150_read_event_value,
|
|
|
|
.write_event_value = &ad7150_write_event_value,
|
2011-05-18 13:42:37 +00:00
|
|
|
};
|
2011-09-02 16:25:20 +00:00
|
|
|
|
2021-03-14 18:14:53 +00:00
|
|
|
static const struct iio_info ad7150_info_no_irq = {
|
|
|
|
.read_raw = &ad7150_read_raw,
|
|
|
|
};
|
|
|
|
|
2021-03-14 18:15:06 +00:00
|
|
|
static void ad7150_reg_disable(void *data)
|
|
|
|
{
|
|
|
|
struct regulator *reg = data;
|
|
|
|
|
|
|
|
regulator_disable(reg);
|
|
|
|
}
|
|
|
|
|
2012-11-19 18:21:57 +00:00
|
|
|
static int ad7150_probe(struct i2c_client *client,
|
2015-12-29 11:27:31 +00:00
|
|
|
const struct i2c_device_id *id)
|
2010-10-28 01:43:53 +00:00
|
|
|
{
|
2011-06-27 12:07:21 +00:00
|
|
|
struct ad7150_chip_info *chip;
|
|
|
|
struct iio_dev *indio_dev;
|
2021-03-14 18:15:06 +00:00
|
|
|
struct regulator *reg;
|
2021-03-14 18:15:02 +00:00
|
|
|
int ret;
|
2011-06-27 12:07:21 +00:00
|
|
|
|
2013-08-24 19:24:00 +00:00
|
|
|
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
|
|
|
|
if (!indio_dev)
|
|
|
|
return -ENOMEM;
|
2021-03-14 18:14:55 +00:00
|
|
|
|
2011-06-27 12:07:21 +00:00
|
|
|
chip = iio_priv(indio_dev);
|
2011-09-02 16:25:20 +00:00
|
|
|
mutex_init(&chip->state_lock);
|
2010-10-28 01:43:53 +00:00
|
|
|
chip->client = client;
|
|
|
|
|
2011-06-27 12:07:21 +00:00
|
|
|
indio_dev->name = id->name;
|
2011-05-18 13:42:37 +00:00
|
|
|
|
2011-06-27 12:07:21 +00:00
|
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
2010-10-28 01:43:53 +00:00
|
|
|
|
2021-03-14 18:15:06 +00:00
|
|
|
reg = devm_regulator_get(&client->dev, "vdd");
|
|
|
|
if (IS_ERR(reg))
|
|
|
|
return PTR_ERR(reg);
|
|
|
|
|
|
|
|
ret = regulator_enable(reg);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = devm_add_action_or_reset(&client->dev, ad7150_reg_disable, reg);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2021-03-14 18:14:59 +00:00
|
|
|
chip->interrupts[0] = fwnode_irq_get(dev_fwnode(&client->dev), 0);
|
|
|
|
if (chip->interrupts[0] < 0)
|
|
|
|
return chip->interrupts[0];
|
|
|
|
if (id->driver_data == AD7150) {
|
|
|
|
chip->interrupts[1] = fwnode_irq_get(dev_fwnode(&client->dev), 1);
|
|
|
|
if (chip->interrupts[1] < 0)
|
|
|
|
return chip->interrupts[1];
|
|
|
|
}
|
|
|
|
if (chip->interrupts[0] &&
|
|
|
|
(id->driver_data == AD7151 || chip->interrupts[1])) {
|
|
|
|
irq_set_status_flags(chip->interrupts[0], IRQ_NOAUTOEN);
|
|
|
|
ret = devm_request_threaded_irq(&client->dev,
|
|
|
|
chip->interrupts[0],
|
|
|
|
NULL,
|
|
|
|
&ad7150_event_handler_ch1,
|
|
|
|
IRQF_TRIGGER_RISING |
|
|
|
|
IRQF_ONESHOT,
|
|
|
|
"ad7150_irq1",
|
|
|
|
indio_dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2021-03-14 18:14:53 +00:00
|
|
|
indio_dev->info = &ad7150_info;
|
|
|
|
switch (id->driver_data) {
|
|
|
|
case AD7150:
|
|
|
|
indio_dev->channels = ad7150_channels;
|
|
|
|
indio_dev->num_channels = ARRAY_SIZE(ad7150_channels);
|
2021-03-14 18:14:59 +00:00
|
|
|
irq_set_status_flags(chip->interrupts[1], IRQ_NOAUTOEN);
|
|
|
|
ret = devm_request_threaded_irq(&client->dev,
|
|
|
|
chip->interrupts[1],
|
|
|
|
NULL,
|
|
|
|
&ad7150_event_handler_ch2,
|
|
|
|
IRQF_TRIGGER_RISING |
|
|
|
|
IRQF_ONESHOT,
|
|
|
|
"ad7150_irq2",
|
|
|
|
indio_dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2021-03-14 18:14:53 +00:00
|
|
|
break;
|
|
|
|
case AD7151:
|
|
|
|
indio_dev->channels = ad7151_channels;
|
|
|
|
indio_dev->num_channels = ARRAY_SIZE(ad7151_channels);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
} else {
|
|
|
|
indio_dev->info = &ad7150_info_no_irq;
|
|
|
|
switch (id->driver_data) {
|
|
|
|
case AD7150:
|
|
|
|
indio_dev->channels = ad7150_channels_no_irq;
|
2021-03-14 18:14:59 +00:00
|
|
|
indio_dev->num_channels =
|
|
|
|
ARRAY_SIZE(ad7150_channels_no_irq);
|
2021-03-14 18:14:53 +00:00
|
|
|
break;
|
|
|
|
case AD7151:
|
|
|
|
indio_dev->channels = ad7151_channels_no_irq;
|
2021-03-14 18:14:59 +00:00
|
|
|
indio_dev->num_channels =
|
|
|
|
ARRAY_SIZE(ad7151_channels_no_irq);
|
2021-03-14 18:14:53 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2010-10-28 01:43:53 +00:00
|
|
|
}
|
|
|
|
|
2021-03-14 18:14:55 +00:00
|
|
|
return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
|
2010-10-28 01:43:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_device_id ad7150_id[] = {
|
2021-03-14 18:14:53 +00:00
|
|
|
{ "ad7150", AD7150 },
|
|
|
|
{ "ad7151", AD7151 },
|
|
|
|
{ "ad7156", AD7150 },
|
2010-10-28 01:43:53 +00:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(i2c, ad7150_id);
|
|
|
|
|
2021-03-14 18:15:07 +00:00
|
|
|
static const struct of_device_id ad7150_of_match[] = {
|
|
|
|
{ "adi,ad7150" },
|
|
|
|
{ "adi,ad7151" },
|
|
|
|
{ "adi,ad7156" },
|
|
|
|
{}
|
|
|
|
};
|
2010-10-28 01:43:53 +00:00
|
|
|
static struct i2c_driver ad7150_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "ad7150",
|
2021-03-14 18:15:07 +00:00
|
|
|
.of_match_table = ad7150_of_match,
|
2010-10-28 01:43:53 +00:00
|
|
|
},
|
|
|
|
.probe = ad7150_probe,
|
|
|
|
.id_table = ad7150_id,
|
|
|
|
};
|
2011-11-16 09:13:38 +00:00
|
|
|
module_i2c_driver(ad7150_driver);
|
2010-10-28 01:43:53 +00:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
|
2011-09-02 16:25:22 +00:00
|
|
|
MODULE_DESCRIPTION("Analog Devices AD7150/1/6 capacitive sensor driver");
|
2010-10-28 01:43:53 +00:00
|
|
|
MODULE_LICENSE("GPL v2");
|