2015-07-28 14:33:04 +00:00
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/*
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* netup_unidvb_spi.c
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*
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* Internal SPI driver for NetUP Universal Dual DVB-CI
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*
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* Copyright (C) 2014 NetUP Inc.
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* Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
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* Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "netup_unidvb.h"
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/mtd/partitions.h>
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#include <mtd/mtd-abi.h>
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#define NETUP_SPI_CTRL_IRQ 0x1000
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#define NETUP_SPI_CTRL_IMASK 0x2000
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#define NETUP_SPI_CTRL_START 0x8000
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#define NETUP_SPI_CTRL_LAST_CS 0x4000
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#define NETUP_SPI_TIMEOUT 6000
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enum netup_spi_state {
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SPI_STATE_START,
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SPI_STATE_DONE,
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};
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struct netup_spi_regs {
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__u8 data[1024];
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__le16 control_stat;
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__le16 clock_divider;
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} __packed __aligned(1);
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struct netup_spi {
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struct device *dev;
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struct spi_master *master;
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2015-10-01 21:49:29 +00:00
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struct netup_spi_regs __iomem *regs;
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2015-07-28 14:33:04 +00:00
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u8 __iomem *mmio;
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spinlock_t lock;
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wait_queue_head_t waitq;
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enum netup_spi_state state;
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};
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static char netup_spi_name[64] = "fpga";
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static struct mtd_partition netup_spi_flash_partitions = {
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.name = netup_spi_name,
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.size = 0x1000000, /* 16MB */
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.offset = 0,
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.mask_flags = MTD_CAP_ROM
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};
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static struct flash_platform_data spi_flash_data = {
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.name = "netup0_m25p128",
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.parts = &netup_spi_flash_partitions,
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.nr_parts = 1,
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};
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static struct spi_board_info netup_spi_board = {
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.modalias = "m25p128",
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.max_speed_hz = 11000000,
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.chip_select = 0,
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.mode = SPI_MODE_0,
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.platform_data = &spi_flash_data,
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};
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irqreturn_t netup_spi_interrupt(struct netup_spi *spi)
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{
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u16 reg;
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unsigned long flags;
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2015-09-25 07:56:21 +00:00
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if (!spi)
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2015-07-28 14:33:04 +00:00
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return IRQ_NONE;
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2015-09-25 07:56:21 +00:00
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2015-07-28 14:33:04 +00:00
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spin_lock_irqsave(&spi->lock, flags);
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reg = readw(&spi->regs->control_stat);
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if (!(reg & NETUP_SPI_CTRL_IRQ)) {
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spin_unlock_irqrestore(&spi->lock, flags);
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dev_dbg(&spi->master->dev,
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"%s(): not mine interrupt\n", __func__);
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return IRQ_NONE;
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}
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writew(reg | NETUP_SPI_CTRL_IRQ, &spi->regs->control_stat);
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reg = readw(&spi->regs->control_stat);
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writew(reg & ~NETUP_SPI_CTRL_IMASK, &spi->regs->control_stat);
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spi->state = SPI_STATE_DONE;
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wake_up(&spi->waitq);
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spin_unlock_irqrestore(&spi->lock, flags);
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dev_dbg(&spi->master->dev,
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"%s(): SPI interrupt handled\n", __func__);
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return IRQ_HANDLED;
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}
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static int netup_spi_transfer(struct spi_master *master,
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struct spi_message *msg)
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{
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struct netup_spi *spi = spi_master_get_devdata(master);
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struct spi_transfer *t;
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int result = 0;
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u32 tr_size;
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/* reset CS */
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writew(NETUP_SPI_CTRL_LAST_CS, &spi->regs->control_stat);
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writew(0, &spi->regs->control_stat);
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list_for_each_entry(t, &msg->transfers, transfer_list) {
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tr_size = t->len;
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while (tr_size) {
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u32 frag_offset = t->len - tr_size;
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u32 frag_size = (tr_size > sizeof(spi->regs->data)) ?
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sizeof(spi->regs->data) : tr_size;
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int frag_last = 0;
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if (list_is_last(&t->transfer_list,
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&msg->transfers) &&
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frag_offset + frag_size == t->len) {
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frag_last = 1;
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}
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if (t->tx_buf) {
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memcpy_toio(spi->regs->data,
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t->tx_buf + frag_offset,
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frag_size);
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} else {
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memset_io(spi->regs->data,
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0, frag_size);
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}
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spi->state = SPI_STATE_START;
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writew((frag_size & 0x3ff) |
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NETUP_SPI_CTRL_IMASK |
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NETUP_SPI_CTRL_START |
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(frag_last ? NETUP_SPI_CTRL_LAST_CS : 0),
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&spi->regs->control_stat);
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dev_dbg(&spi->master->dev,
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"%s(): control_stat 0x%04x\n",
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__func__, readw(&spi->regs->control_stat));
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wait_event_timeout(spi->waitq,
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spi->state != SPI_STATE_START,
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msecs_to_jiffies(NETUP_SPI_TIMEOUT));
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if (spi->state == SPI_STATE_DONE) {
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if (t->rx_buf) {
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memcpy_fromio(t->rx_buf + frag_offset,
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spi->regs->data, frag_size);
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}
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} else {
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if (spi->state == SPI_STATE_START) {
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dev_dbg(&spi->master->dev,
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"%s(): transfer timeout\n",
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__func__);
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} else {
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dev_dbg(&spi->master->dev,
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"%s(): invalid state %d\n",
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__func__, spi->state);
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}
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result = -EIO;
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goto done;
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}
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tr_size -= frag_size;
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msg->actual_length += frag_size;
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}
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}
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done:
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msg->status = result;
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spi_finalize_current_message(master);
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return result;
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}
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static int netup_spi_setup(struct spi_device *spi)
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{
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return 0;
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}
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int netup_spi_init(struct netup_unidvb_dev *ndev)
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{
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struct spi_master *master;
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struct netup_spi *nspi;
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master = spi_alloc_master(&ndev->pci_dev->dev,
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sizeof(struct netup_spi));
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if (!master) {
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dev_err(&ndev->pci_dev->dev,
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"%s(): unable to alloc SPI master\n", __func__);
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return -EINVAL;
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}
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nspi = spi_master_get_devdata(master);
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
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master->bus_num = -1;
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master->num_chipselect = 1;
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master->transfer_one_message = netup_spi_transfer;
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master->setup = netup_spi_setup;
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spin_lock_init(&nspi->lock);
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init_waitqueue_head(&nspi->waitq);
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nspi->master = master;
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2015-10-01 21:49:29 +00:00
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nspi->regs = (struct netup_spi_regs __iomem *)(ndev->bmmio0 + 0x4000);
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2015-07-28 14:33:04 +00:00
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writew(2, &nspi->regs->clock_divider);
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writew(NETUP_UNIDVB_IRQ_SPI, ndev->bmmio0 + REG_IMASK_SET);
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ndev->spi = nspi;
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if (spi_register_master(master)) {
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ndev->spi = NULL;
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dev_err(&ndev->pci_dev->dev,
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"%s(): unable to register SPI bus\n", __func__);
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return -EINVAL;
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}
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snprintf(netup_spi_name,
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sizeof(netup_spi_name),
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"fpga_%02x:%02x.%01x",
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ndev->pci_bus,
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ndev->pci_slot,
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ndev->pci_func);
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if (!spi_new_device(master, &netup_spi_board)) {
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ndev->spi = NULL;
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dev_err(&ndev->pci_dev->dev,
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"%s(): unable to create SPI device\n", __func__);
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return -EINVAL;
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}
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dev_dbg(&ndev->pci_dev->dev, "%s(): SPI init OK\n", __func__);
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return 0;
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}
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void netup_spi_release(struct netup_unidvb_dev *ndev)
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{
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u16 reg;
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unsigned long flags;
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struct netup_spi *spi = ndev->spi;
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2015-09-25 07:56:21 +00:00
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if (!spi)
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2015-07-28 14:33:04 +00:00
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return;
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2015-09-25 07:56:21 +00:00
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2015-07-28 14:33:04 +00:00
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spin_lock_irqsave(&spi->lock, flags);
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reg = readw(&spi->regs->control_stat);
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writew(reg | NETUP_SPI_CTRL_IRQ, &spi->regs->control_stat);
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reg = readw(&spi->regs->control_stat);
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writew(reg & ~NETUP_SPI_CTRL_IMASK, &spi->regs->control_stat);
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spin_unlock_irqrestore(&spi->lock, flags);
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spi_unregister_master(spi->master);
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ndev->spi = NULL;
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}
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