2018-06-28 17:05:13 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef S390_ISM_H
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#define S390_ISM_H
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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2023-01-23 18:17:47 +00:00
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#include <linux/ism.h>
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2018-06-28 17:05:13 +00:00
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#include <net/smc.h>
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2019-04-23 09:57:46 +00:00
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#include <asm/pci_insn.h>
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2018-06-28 17:05:13 +00:00
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#define UTIL_STR_LEN 16
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/*
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* Do not use the first word of the DMB bits to ensure 8 byte aligned access.
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*/
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#define ISM_DMB_WORD_OFFSET 1
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#define ISM_DMB_BIT_OFFSET (ISM_DMB_WORD_OFFSET * 32)
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#define ISM_REG_SBA 0x1
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#define ISM_REG_IEQ 0x2
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#define ISM_READ_GID 0x3
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#define ISM_ADD_VLAN_ID 0x4
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#define ISM_DEL_VLAN_ID 0x5
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#define ISM_SET_VLAN 0x6
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#define ISM_RESET_VLAN 0x7
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#define ISM_QUERY_INFO 0x8
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#define ISM_QUERY_RGID 0x9
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#define ISM_REG_DMB 0xA
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#define ISM_UNREG_DMB 0xB
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#define ISM_SIGNAL_IEQ 0xE
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#define ISM_UNREG_SBA 0x11
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#define ISM_UNREG_IEQ 0x12
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struct ism_req_hdr {
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u32 cmd;
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u16 : 16;
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u16 len;
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};
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struct ism_resp_hdr {
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u32 cmd;
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u16 ret;
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u16 len;
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};
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union ism_reg_sba {
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struct {
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struct ism_req_hdr hdr;
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u64 sba;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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} response;
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} __aligned(16);
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union ism_reg_ieq {
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struct {
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struct ism_req_hdr hdr;
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u64 ieq;
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u64 len;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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} response;
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} __aligned(16);
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union ism_read_gid {
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struct {
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struct ism_req_hdr hdr;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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u64 gid;
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} response;
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} __aligned(16);
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union ism_qi {
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struct {
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struct ism_req_hdr hdr;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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u32 version;
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u32 max_len;
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u64 ism_state;
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u64 my_gid;
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u64 sba;
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u64 ieq;
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u32 ieq_len;
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u32 : 32;
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u32 dmbs_owned;
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u32 dmbs_used;
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u32 vlan_required;
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u32 vlan_nr_ids;
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u16 vlan_id[64];
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} response;
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} __aligned(64);
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union ism_query_rgid {
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struct {
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struct ism_req_hdr hdr;
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u64 rgid;
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u32 vlan_valid;
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u32 vlan_id;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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} response;
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} __aligned(16);
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union ism_reg_dmb {
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struct {
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struct ism_req_hdr hdr;
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u64 dmb;
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u32 dmb_len;
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u32 sba_idx;
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u32 vlan_valid;
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u32 vlan_id;
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u64 rgid;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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u64 dmb_tok;
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} response;
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} __aligned(32);
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union ism_sig_ieq {
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struct {
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struct ism_req_hdr hdr;
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u64 rgid;
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u32 trigger_irq;
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u32 event_code;
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u64 info;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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} response;
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} __aligned(32);
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union ism_unreg_dmb {
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struct {
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struct ism_req_hdr hdr;
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u64 dmb_tok;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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} response;
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} __aligned(16);
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union ism_cmd_simple {
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struct {
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struct ism_req_hdr hdr;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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} response;
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} __aligned(8);
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union ism_set_vlan_id {
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struct {
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struct ism_req_hdr hdr;
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u64 vlan_id;
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} request;
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struct {
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struct ism_resp_hdr hdr;
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} response;
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} __aligned(16);
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struct ism_eq_header {
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u64 idx;
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u64 ieq_len;
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u64 entry_len;
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u64 : 64;
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};
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struct ism_eq {
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struct ism_eq_header header;
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2023-01-23 18:17:48 +00:00
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struct ism_event entry[15];
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2018-06-28 17:05:13 +00:00
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};
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struct ism_sba {
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u32 s : 1; /* summary bit */
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u32 e : 1; /* event bit */
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u32 : 30;
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u32 dmb_bits[ISM_NR_DMBS / 32];
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u32 reserved[3];
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u16 dmbe_mask[ISM_NR_DMBS];
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};
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#define ISM_CREATE_REQ(dmb, idx, sf, offset) \
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((dmb) | (idx) << 24 | (sf) << 23 | (offset))
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2019-04-23 09:57:46 +00:00
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static inline void __ism_read_cmd(struct ism_dev *ism, void *data,
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unsigned long offset, unsigned long len)
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{
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struct zpci_dev *zdev = to_zpci(ism->pdev);
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u64 req = ZPCI_CREATE_REQ(zdev->fh, 2, 8);
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while (len > 0) {
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__zpci_load(data, req, offset);
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offset += 8;
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data += 8;
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len -= 8;
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}
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}
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static inline void __ism_write_cmd(struct ism_dev *ism, void *data,
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unsigned long offset, unsigned long len)
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{
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struct zpci_dev *zdev = to_zpci(ism->pdev);
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u64 req = ZPCI_CREATE_REQ(zdev->fh, 2, len);
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if (len)
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__zpci_store_block(data, req, offset);
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}
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2018-06-28 17:05:13 +00:00
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static inline int __ism_move(struct ism_dev *ism, u64 dmb_req, void *data,
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unsigned int size)
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{
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struct zpci_dev *zdev = to_zpci(ism->pdev);
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u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, size);
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2019-04-14 14:25:54 +00:00
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return __zpci_store_block(data, req, dmb_req);
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2018-06-28 17:05:13 +00:00
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}
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#endif /* S390_ISM_H */
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