2012-11-19 11:09:40 +00:00
|
|
|
/*
|
|
|
|
* Copyright 2012 Maxime Ripard
|
|
|
|
*
|
|
|
|
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
|
|
*
|
|
|
|
* The code contained herein is licensed under the GNU General Public
|
|
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
|
|
* Version 2 or later at the following locations:
|
|
|
|
*
|
|
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
|
|
*/
|
|
|
|
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
|
|
|
|
/ {
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
|
|
|
cpus {
|
|
|
|
cpu@0 {
|
|
|
|
compatible = "arm,cortex-a8";
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
clocks {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
osc: oscillator {
|
|
|
|
#clock-cells = <0>;
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
clock-frequency = <24000000>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
soc {
|
|
|
|
compatible = "simple-bus";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
reg = <0x01c20000 0x300000>;
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
timer@01c20c00 {
|
|
|
|
compatible = "allwinner,sunxi-timer";
|
2012-11-19 17:57:08 +00:00
|
|
|
reg = <0x01c20c00 0x90>;
|
2012-11-19 11:09:40 +00:00
|
|
|
interrupts = <22>;
|
|
|
|
clocks = <&osc>;
|
|
|
|
};
|
|
|
|
|
2012-11-19 17:57:08 +00:00
|
|
|
wdt: watchdog@01c20c90 {
|
|
|
|
compatible = "allwinner,sunxi-wdt";
|
|
|
|
reg = <0x01c20c90 0x10>;
|
|
|
|
};
|
|
|
|
|
2012-11-19 11:09:40 +00:00
|
|
|
intc: interrupt-controller@01c20400 {
|
|
|
|
compatible = "allwinner,sunxi-ic";
|
|
|
|
reg = <0x01c20400 0x400>;
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
};
|
|
|
|
|
2012-11-19 11:09:42 +00:00
|
|
|
uart0: uart@01c28000 {
|
2013-01-14 18:53:54 +00:00
|
|
|
compatible = "snps,dw-apb-uart";
|
2012-11-19 11:09:42 +00:00
|
|
|
reg = <0x01c28000 0x400>;
|
|
|
|
interrupts = <1>;
|
|
|
|
reg-shift = <2>;
|
2013-01-14 18:53:54 +00:00
|
|
|
reg-io-width = <4>;
|
2012-11-19 11:09:42 +00:00
|
|
|
clock-frequency = <24000000>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2012-11-19 11:09:40 +00:00
|
|
|
uart1: uart@01c28400 {
|
2013-01-14 18:53:54 +00:00
|
|
|
compatible = "snps,dw-apb-uart";
|
2012-11-19 11:09:40 +00:00
|
|
|
reg = <0x01c28400 0x400>;
|
|
|
|
interrupts = <2>;
|
|
|
|
reg-shift = <2>;
|
2013-01-14 18:53:54 +00:00
|
|
|
reg-io-width = <4>;
|
2012-11-19 11:09:40 +00:00
|
|
|
clock-frequency = <24000000>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|